78 int mec_hal_bcl_soft_reset(struct mec_bcl_regs *regs, uint8_t enable)  in mec_hal_bcl_soft_reset()  argument
81     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_soft_reset()
87         regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_SRST_Pos);  in mec_hal_bcl_soft_reset()
89         regs->STATUS = (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos);  in mec_hal_bcl_soft_reset()
95 int mec_hal_bcl_get_freq(struct mec_bcl_regs *regs, uint32_t *freq_hz)  in mec_hal_bcl_get_freq()  argument
98     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_get_freq()
106     uint32_t fdiv = (regs->CLKSEL & 0xffu);  in mec_hal_bcl_get_freq()
113 bool mec_hal_bcl_is_busy(struct mec_bcl_regs *regs)  in mec_hal_bcl_is_busy()  argument
116     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_is_busy()
121     if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) {  in mec_hal_bcl_is_busy()
129 int mec_hal_bcl_set_freq(struct mec_bcl_regs *regs, uint32_t freq_hz)  in mec_hal_bcl_set_freq()  argument
134     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_set_freq()
139     if (mec_hal_bcl_is_busy(regs)) {  in mec_hal_bcl_set_freq()
152     regs->CLKSEL = (regs->CLKSEL & 0xffffff00u) | (clkdiv & 0xffu);  in mec_hal_bcl_set_freq()
157 bool mec_hal_bcl_is_error(struct mec_bcl_regs *regs)  in mec_hal_bcl_is_error()  argument
160     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_is_error()
165     if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BCERR_Pos)) {  in mec_hal_bcl_is_error()
172 int mec_hal_bcl_clear_error(struct mec_bcl_regs *regs)  in mec_hal_bcl_clear_error()  argument
175     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_clear_error()
180     regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCERR_Pos);  in mec_hal_bcl_clear_error()
190 int mec_hal_bcl_clear_not_busy(struct mec_bcl_regs *regs)  in mec_hal_bcl_clear_not_busy()  argument
193     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_clear_not_busy()
197     (void)regs;  in mec_hal_bcl_clear_not_busy()
205 int mec_hal_bcl_intr_ctrl(struct mec_bcl_regs *regs, uint8_t msk, uint8_t enable)  in mec_hal_bcl_intr_ctrl()  argument
210     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_intr_ctrl()
233     regs->STATUS = (regs->STATUS & (uint32_t)~regmsk) | ien;  in mec_hal_bcl_intr_ctrl()
238 int mec_hal_bcl_get_target_address(struct mec_bcl_regs *regs, uint8_t *target_address)  in mec_hal_bcl_get_target_address()  argument
241     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_get_target_address()
247         *target_address = (uint8_t)(regs->DESTA & 0xffu);  in mec_hal_bcl_get_target_address()
253 int mec_hal_bcl_set_target_address(struct mec_bcl_regs *regs, uint8_t target_address)  in mec_hal_bcl_set_target_address()  argument
256     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_set_target_address()
261     regs->DESTA = target_address;  in mec_hal_bcl_set_target_address()
267 int mec_hal_bcl_get_data(struct mec_bcl_regs *regs, uint8_t *data)  in mec_hal_bcl_get_data()  argument
270     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_get_data()
276         *data = (uint8_t)regs->DATA;  in mec_hal_bcl_get_data()
282 int mec_hal_bcl_set_data(struct mec_bcl_regs *regs, uint8_t data)  in mec_hal_bcl_set_data()  argument
285     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_set_data()
290     regs->DATA = data;  in mec_hal_bcl_set_data()
295 int mec_hal_bcl_start(struct mec_bcl_regs *regs, uint8_t target_reg, uint8_t wrdata, uint32_t flags)  in mec_hal_bcl_start()  argument
300     if ((uintptr_t)regs != (uintptr_t)MEC_BCL0_BASE) {  in mec_hal_bcl_start()
305     if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) {  in mec_hal_bcl_start()
309     regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCERR_Pos);  in mec_hal_bcl_start()
313         regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BERR_IEN_Pos);  in mec_hal_bcl_start()
317     regs->DESTA = target_reg;  in mec_hal_bcl_start()
320         regs->DATA; /* first read of data register triggers transmit of read packet */  in mec_hal_bcl_start()
322         regs->DATA = wrdata; /* write data register triggers transmit of write packet */  in mec_hal_bcl_start()
330         regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCLR_IEN_Pos);  in mec_hal_bcl_start()