Lines Matching refs:regs
23 uint32_t _i3c_intr_sts_get(struct mec_i3c_host_regs *regs) in _i3c_intr_sts_get() argument
25 return regs->INTR_STS; in _i3c_intr_sts_get()
33 void _i3c_intr_sts_clear(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_clear() argument
35 regs->INTR_STS = mask; in _i3c_intr_sts_clear()
43 void _i3c_intr_sts_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sts_enable() argument
45 regs->INTR_EN = mask; in _i3c_intr_sts_enable()
53 void _i3c_intr_IBI_enable(struct mec_i3c_host_regs *regs) in _i3c_intr_IBI_enable() argument
55 regs->INTR_EN |= sbit_IBI_THLD_STS; in _i3c_intr_IBI_enable()
57 regs->INTR_SIG_EN |= sbit_IBI_THLD_STS; in _i3c_intr_IBI_enable()
65 void _i3c_intr_IBI_disable(struct mec_i3c_host_regs *regs) in _i3c_intr_IBI_disable() argument
67 regs->INTR_EN &= (uint32_t)~sbit_IBI_THLD_STS; in _i3c_intr_IBI_disable()
69 regs->INTR_SIG_EN &= (uint32_t)~sbit_IBI_THLD_STS; in _i3c_intr_IBI_disable()
77 void _i3c_intr_thresholds_tx_enable(struct mec_i3c_host_regs *regs) in _i3c_intr_thresholds_tx_enable() argument
79 regs->INTR_EN |= sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_enable()
81 regs->INTR_SIG_EN |= sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_enable()
89 void _i3c_intr_thresholds_tx_disable(struct mec_i3c_host_regs *regs) in _i3c_intr_thresholds_tx_disable() argument
91 regs->INTR_EN &= (uint32_t)~sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_disable()
93 regs->INTR_SIG_EN &= (uint32_t)~sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_disable()
101 void _i3c_intr_thresholds_rx_enable(struct mec_i3c_host_regs *regs) in _i3c_intr_thresholds_rx_enable() argument
103 regs->INTR_EN |= sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_enable()
105 regs->INTR_SIG_EN |= sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_enable()
113 void _i3c_intr_thresholds_rx_disable(struct mec_i3c_host_regs *regs) in _i3c_intr_thresholds_rx_disable() argument
115 regs->INTR_EN &= (uint32_t)~sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_disable()
117 regs->INTR_SIG_EN &= (uint32_t)~sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_disable()
125 void _i3c_intr_sgnl_enable(struct mec_i3c_host_regs *regs, uint32_t mask) in _i3c_intr_sgnl_enable() argument
127 regs->INTR_SIG_EN = mask; in _i3c_intr_sgnl_enable()
135 void _i3c_resp_queue_threshold_set(struct mec_i3c_host_regs *regs, uint8_t threshold) in _i3c_resp_queue_threshold_set() argument
139 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_RESP_QUEUE_BITPOS); in _i3c_resp_queue_threshold_set()
140 regs->QUE_THLD_CTRL |= (threshold << QUEUE_THLD_RESP_QUEUE_BITPOS); in _i3c_resp_queue_threshold_set()
149 uint8_t _i3c_resp_buf_level_get(struct mec_i3c_host_regs *regs) in _i3c_resp_buf_level_get() argument
153 level = (regs->QUE_STS_LVL >> Q_STS_LVL_RESP_BUFFER_BIT_POS) & 0xFF; in _i3c_resp_buf_level_get()
163 uint8_t _i3c_ibi_status_count_get(struct mec_i3c_host_regs *regs) in _i3c_ibi_status_count_get() argument
167 level = (regs->QUE_STS_LVL >> Q_STS_LVL_IBI_STS_CNT_BIT_POS) & 0x1F; in _i3c_ibi_status_count_get()
177 uint32_t _i3c_ibi_queue_status_get(struct mec_i3c_host_regs *regs) in _i3c_ibi_queue_status_get() argument
181 queue_sts = regs->IBI_QUE_STS; in _i3c_ibi_queue_status_get()
191 uint8_t _i3c_response_sts_get(struct mec_i3c_host_regs *regs, uint16_t *len, uint8_t *tid) in _i3c_response_sts_get() argument
196 response = regs->RESP; in _i3c_response_sts_get()
211 uint8_t _i3c_tgt_response_sts_get(struct mec_i3c_sec_regs *regs, uint16_t *len, uint8_t *tid, in _i3c_tgt_response_sts_get() argument
217 response = regs->RESP; in _i3c_tgt_response_sts_get()
238 void _i3c_cmd_queue_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_cmd_queue_threshold_set() argument
240 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_CMD_QUEUE_BITPOS); in _i3c_cmd_queue_threshold_set()
241 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_CMD_QUEUE_BITPOS); in _i3c_cmd_queue_threshold_set()
249 void _i3c_ibi_data_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_ibi_data_threshold_set() argument
251 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_IBI_DATA_BITPOS); in _i3c_ibi_data_threshold_set()
252 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_DATA_BITPOS); in _i3c_ibi_data_threshold_set()
260 void _i3c_ibi_status_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_ibi_status_threshold_set() argument
262 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_IBI_STATUS_BITPOS); in _i3c_ibi_status_threshold_set()
263 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_STATUS_BITPOS); in _i3c_ibi_status_threshold_set()
271 void _i3c_tx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_tx_buf_threshold_set() argument
273 regs->DB_THLD_CTRL &= (uint32_t)~(0xFFu << DATA_BUF_THLD_TX_FIFO_EMPTY_BITPOS); in _i3c_tx_buf_threshold_set()
274 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_TX_FIFO_EMPTY_BITPOS); in _i3c_tx_buf_threshold_set()
282 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_rx_buf_threshold_set() argument
284 regs->DB_THLD_CTRL &= (uint32_t)~(0xFFu << DATA_BUF_THLD_RX_FIFO_BITPOS); in _i3c_rx_buf_threshold_set()
285 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_RX_FIFO_BITPOS); in _i3c_rx_buf_threshold_set()
293 void _i3c_tx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_tx_start_threshold_set() argument
295 regs->DB_THLD_CTRL &= (uint32_t)~(0xFFu << DATA_BUF_THLD_TX_FIFO_START_BITPOS); in _i3c_tx_start_threshold_set()
296 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_TX_FIFO_START_BITPOS); in _i3c_tx_start_threshold_set()
304 void _i3c_rx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_rx_start_threshold_set() argument
306 regs->DB_THLD_CTRL &= ~(0xFF << DATA_BUF_THLD_RX_FIFO_START_BITPOS); in _i3c_rx_start_threshold_set()
307 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_RX_FIFO_START_BITPOS); in _i3c_rx_start_threshold_set()
315 void _i3c_notify_sir_reject(struct mec_i3c_host_regs *regs, bool opt) in _i3c_notify_sir_reject() argument
317 regs->IBI_QUE_CTRL = (opt << IBI_QUEUE_CTRL_SIR_REJ_BITPOS); in _i3c_notify_sir_reject()
325 void _i3c_notify_mr_reject(struct mec_i3c_host_regs *regs, bool opt) in _i3c_notify_mr_reject() argument
327 regs->IBI_QUE_CTRL = (opt << IBI_QUEUE_CTRL_MR_REJ_BITPOS); in _i3c_notify_mr_reject()
335 void _i3c_notify_hj_reject(struct mec_i3c_host_regs *regs, bool opt) in _i3c_notify_hj_reject() argument
337 regs->IBI_QUE_CTRL = (opt << IBI_QUEUE_CTRL_HJ_REJ_BITPOS); in _i3c_notify_hj_reject()
346 void _i3c_dynamic_addr_set(struct mec_i3c_host_regs *regs, uint8_t address) in _i3c_dynamic_addr_set() argument
348 regs->DEV_ADDR = ((address & 0x7F) << DEVICE_ADDR_DYNAMIC_ADDR_BITPOS) | in _i3c_dynamic_addr_set()
358 void _i3c_static_addr_set(struct mec_i3c_host_regs *regs, uint8_t address) in _i3c_static_addr_set() argument
362 reg_val = regs->DEV_ADDR; in _i3c_static_addr_set()
366 regs->DEV_ADDR = reg_val; in _i3c_static_addr_set()
375 void _i3c_operation_mode_set(struct mec_i3c_host_regs *regs, uint8_t mode) in _i3c_operation_mode_set() argument
377 regs->DEV_EXT_CTRL = mode & 0x1; in _i3c_operation_mode_set()
386 void _i3c_enable(struct mec_i3c_host_regs *regs, uint8_t mode, bool enable_dma) in _i3c_enable() argument
391 val = regs->DEV_CTRL; in _i3c_enable()
405 regs->DEV_CTRL = val; in _i3c_enable()
413 void _i3c_disable(struct mec_i3c_host_regs *regs) in _i3c_disable() argument
418 val = regs->DEV_CTRL; in _i3c_disable()
422 regs->DEV_CTRL = val; in _i3c_disable()
430 void _i3c_resume(struct mec_i3c_host_regs *regs) in _i3c_resume() argument
432 regs->DEV_CTRL |= sbit_RESUME; in _i3c_resume()
440 void _i3c_xfer_err_sts_clr(struct mec_i3c_host_regs *regs) in _i3c_xfer_err_sts_clr() argument
444 sts = regs->INTR_STS; in _i3c_xfer_err_sts_clr()
448 regs->INTR_STS = sbit_TRANSFER_ERR_STS; in _i3c_xfer_err_sts_clr()
458 void _i3c_hot_join_disable(struct mec_i3c_host_regs *regs) in _i3c_hot_join_disable() argument
463 val = regs->DEV_CTRL; in _i3c_hot_join_disable()
469 regs->DEV_CTRL = val; in _i3c_hot_join_disable()
478 void _i3c_tgt_hot_join_disable(struct mec_i3c_sec_regs *regs) in _i3c_tgt_hot_join_disable() argument
483 val = regs->TGT_EVT_STS; in _i3c_tgt_hot_join_disable()
487 regs->DEV_CTRL = val; in _i3c_tgt_hot_join_disable()
496 void _i3c_hot_join_enable(struct mec_i3c_host_regs *regs) in _i3c_hot_join_enable() argument
501 val = regs->DEV_CTRL; in _i3c_hot_join_enable()
506 regs->DEV_CTRL = val; in _i3c_hot_join_enable()
515 void _i2c_fm_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns) in _i2c_fm_timing_set() argument
532 regs->SCL_I2C_FM_TM = timing_val; in _i2c_fm_timing_set()
537 regs->BUS_FREE_TM = low_count; in _i2c_fm_timing_set()
546 void _i3c_bus_free_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns) in _i3c_bus_free_timing_set() argument
556 regs->BUS_FREE_TM |= (bus_free_timing_count & 0xffffu); in _i3c_bus_free_timing_set()
565 void _i3c_bus_available_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns) in _i3c_bus_available_timing_set() argument
574 regs->BUS_FREE_TM = (bus_avail_timing_count << 16); in _i3c_bus_available_timing_set()
583 void _i3c_bus_idle_timing_set(struct mec_i3c_sec_regs *regs, uint32_t core_clk_freq_ns) in _i3c_bus_idle_timing_set() argument
592 regs->BUS_IDLE_TM = idle_count; in _i3c_bus_idle_timing_set()
601 void _i3c_sda_hld_switch_delay_timing_set(struct mec_i3c_sec_regs *regs, in _i3c_sda_hld_switch_delay_timing_set() argument
606 regs->SDA_HMSD_TM = (sda_od_pp_switch_dly << SDA_OD_PP_SWITCH_DLY_BITPOS); in _i3c_sda_hld_switch_delay_timing_set()
607 regs->SDA_HMSD_TM |= (sda_pp_od_switch_dly << SDA_PP_OD_SWITCH_DLY_BITPOS); in _i3c_sda_hld_switch_delay_timing_set()
608 regs->SDA_HMSD_TM |= (sda_tx_hold << SDA_TX_HOLD_BITPOS); in _i3c_sda_hld_switch_delay_timing_set()
617 void _i3c_sda_hld_timing_set(struct mec_i3c_host_regs *regs, in _i3c_sda_hld_timing_set() argument
622 reg_value = regs->SDA_HMSD_TM; in _i3c_sda_hld_timing_set()
623 regs->SDA_HMSD_TM = (reg_value & 0xFFF8FFFF) | (sda_tx_hold << SDA_TX_HOLD_BITPOS); in _i3c_sda_hld_timing_set()
632 void _i3c_read_term_bit_low_count_set(struct mec_i3c_host_regs *regs, in _i3c_read_term_bit_low_count_set() argument
637 reg_value = regs->SCL_TBLC_TM; in _i3c_read_term_bit_low_count_set()
638 regs->SCL_TBLC_TM = (reg_value & 0xFFFFFFF0) | (read_term_low_count); in _i3c_read_term_bit_low_count_set()
647 void _i3c_scl_low_mst_tout_set(struct mec_i3c_sec_regs *regs, uint32_t tout_val) in _i3c_scl_low_mst_tout_set() argument
649 regs->SCL_LMST_TM = tout_val; in _i3c_scl_low_mst_tout_set()
657 void _i2c_target_present_set(struct mec_i3c_host_regs *regs) in _i2c_target_present_set() argument
659 regs->DEV_CTRL |= sbit_I2C_TGT_PRESENT; in _i2c_target_present_set()
667 void _i2c_target_present_reset(struct mec_i3c_host_regs *regs) in _i2c_target_present_reset() argument
669 regs->DEV_CTRL &= ~sbit_I2C_TGT_PRESENT; in _i2c_target_present_reset()
678 void _i2c_fmp_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns) in _i2c_fmp_timing_set() argument
695 regs->SCL_I2C_FMP_TM = timing_val; in _i2c_fmp_timing_set()
704 void _i3c_push_pull_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns, in _i3c_push_pull_timing_set() argument
726 regs->SCL_PP_TM = timing_val; in _i3c_push_pull_timing_set()
731 if (!(regs->DEV_CTRL & sbit_I2C_TGT_PRESENT)) in _i3c_push_pull_timing_set()
733 regs->BUS_FREE_TM = low_count; in _i3c_push_pull_timing_set()
745 regs->SCL_ELC_TM = sdr_ext_lcount; in _i3c_push_pull_timing_set()
754 void _i3c_open_drain_timing_set(struct mec_i3c_host_regs *regs, uint32_t core_clk_freq_ns, in _i3c_open_drain_timing_set() argument
778 regs->SCL_OD_TM = timing_val; in _i3c_open_drain_timing_set()
786 void _i3c_host_dma_tx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_dma_tx_burst_length_set() argument
788 regs->HOST_CFG &= (uint32_t)~(0x03u << HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_tx_burst_length_set()
789 regs->HOST_CFG |= (val << HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_tx_burst_length_set()
797 void _i3c_host_dma_rx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_dma_rx_burst_length_set() argument
799 regs->HOST_CFG &= (uint32_t)~(0x03u << HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_rx_burst_length_set()
800 regs->HOST_CFG |= (val << HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_rx_burst_length_set()
808 void _i3c_host_port_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_port_set() argument
810 regs->HOST_CFG &= (uint32_t)~(0x0Fu << HOST_CFG_PORT_SEL_BIT_POS); in _i3c_host_port_set()
811 regs->HOST_CFG |= (val << HOST_CFG_PORT_SEL_BIT_POS); in _i3c_host_port_set()
819 void _i3c_host_stuck_sda_config(struct mec_i3c_host_regs *regs, uint32_t en, uint32_t tout_val) in _i3c_host_stuck_sda_config() argument
821 regs->HOST_CFG &= (uint32_t)~(0x01u << HOST_CFG_STUCK_SDA_EN_BIT_POS); in _i3c_host_stuck_sda_config()
822 regs->HOST_CFG |= (en << HOST_CFG_STUCK_SDA_EN_BIT_POS); in _i3c_host_stuck_sda_config()
824 regs->STK_SDA_TMOUT = tout_val; in _i3c_host_stuck_sda_config()
826 regs->STK_SDA_TMOUT = 0U; in _i3c_host_stuck_sda_config()
835 void _i3c_host_tx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t en, uint32_t tout_val) in _i3c_host_tx_dma_tout_config() argument
837 regs->HOST_CFG &= (uint32_t)~(0x01u << HOST_CFG_TX_DMA_TOUT_BITPOS); in _i3c_host_tx_dma_tout_config()
838 regs->HOST_CFG |= (en << HOST_CFG_TX_DMA_TOUT_BITPOS); in _i3c_host_tx_dma_tout_config()
840 regs->HOST_DMA_TX_TMOUT = tout_val; in _i3c_host_tx_dma_tout_config()
842 regs->HOST_DMA_TX_TMOUT = 0U; in _i3c_host_tx_dma_tout_config()
851 void _i3c_host_rx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t en, uint32_t tout_val) in _i3c_host_rx_dma_tout_config() argument
853 regs->HOST_CFG &= (uint32_t)~(0x01u << HOST_CFG_TX_DMA_TOUT_BITPOS); in _i3c_host_rx_dma_tout_config()
854 regs->HOST_CFG |= (en << HOST_CFG_TX_DMA_TOUT_BITPOS); in _i3c_host_rx_dma_tout_config()
856 regs->HOST_DMA_RX_TMOUT = tout_val; in _i3c_host_rx_dma_tout_config()
858 regs->HOST_DMA_RX_TMOUT = 0U; in _i3c_host_rx_dma_tout_config()
867 void _i3c_sec_host_dma_tx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_dma_tx_burst_length_set() argument
869 regs->SEC_CFG &= (uint32_t)~(0x03u << SEC_HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_tx_burst_length_set()
870 regs->SEC_CFG |= (val << SEC_HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_tx_burst_length_set()
878 void _i3c_sec_host_dma_rx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_dma_rx_burst_length_set() argument
880 regs->SEC_CFG &= (uint32_t)~(0x03u << SEC_HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_rx_burst_length_set()
881 regs->SEC_CFG |= (val << SEC_HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_rx_burst_length_set()
889 void _i3c_sec_host_port_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_port_set() argument
891 regs->SEC_CFG &= (uint32_t)~(0x0Fu << SEC_HOST_CFG_PORT_SEL_BIT_POS); in _i3c_sec_host_port_set()
892 regs->SEC_CFG |= (val << SEC_HOST_CFG_PORT_SEL_BIT_POS); in _i3c_sec_host_port_set()
900 void _i3c_sec_host_stuck_sda_scl_config(struct mec_i3c_sec_regs *regs, uint32_t en, in _i3c_sec_host_stuck_sda_scl_config() argument
903 regs->SEC_CFG &= (uint32_t)~(0x01u << SEC_HOST_CFG_STUCK_SDA_EN_BIT_POS); in _i3c_sec_host_stuck_sda_scl_config()
904 regs->SEC_CFG |= (en << SEC_HOST_CFG_STUCK_SDA_EN_BIT_POS); in _i3c_sec_host_stuck_sda_scl_config()
906 regs->STK_SDA_TMOUT = in _i3c_sec_host_stuck_sda_scl_config()
908 regs->STK_SDA_TMOUT = in _i3c_sec_host_stuck_sda_scl_config()
911 regs->STK_SDA_TMOUT = 0U; in _i3c_sec_host_stuck_sda_scl_config()
920 void _i3c_sec_host_tx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t en, uint32_t tout_val) in _i3c_sec_host_tx_dma_tout_config() argument
923 regs->HOST_DMA_TX_TMOUT = tout_val; in _i3c_sec_host_tx_dma_tout_config()
925 regs->HOST_DMA_TX_TMOUT = 0U; in _i3c_sec_host_tx_dma_tout_config()
934 void _i3c_sec_host_rx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t en, uint32_t tout_val) in _i3c_sec_host_rx_dma_tout_config() argument
937 regs->HOST_DMA_RX_TMOUT = tout_val; in _i3c_sec_host_rx_dma_tout_config()
939 regs->HOST_DMA_RX_TMOUT = 0U; in _i3c_sec_host_rx_dma_tout_config()
948 void _i3c_sec_host_dma_fsm_enable(struct mec_i3c_sec_regs *regs) in _i3c_sec_host_dma_fsm_enable() argument
955 regs->SEC_CFG |= bitmask; in _i3c_sec_host_dma_fsm_enable()
965 void _i3c_dev_addr_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr, in _i3c_dev_addr_table_ptr_get() argument
970 val = regs->DAT_PTR; in _i3c_dev_addr_table_ptr_get()
983 void _i3c_dev_char_table_ptr_get(struct mec_i3c_host_regs *regs, uint16_t *start_addr, in _i3c_dev_char_table_ptr_get() argument
988 val = regs->DCT_PTR; in _i3c_dev_char_table_ptr_get()
999 uint8_t _i3c_dev_operation_mode_get(struct mec_i3c_host_regs *regs) in _i3c_dev_operation_mode_get() argument
1001 return (uint8_t)(regs->DEV_EXT_CTRL & 0x03U); in _i3c_dev_operation_mode_get()
1010 uint8_t _i3c_dev_controller_role_get(struct mec_i3c_host_regs *regs) in _i3c_dev_controller_role_get() argument
1012 return (uint8_t)(regs->PRES_STATE & 0x04U); in _i3c_dev_controller_role_get()
1021 uint8_t _i3c_dev_role_config_get(struct mec_i3c_host_regs *regs) in _i3c_dev_role_config_get() argument
1023 return (uint8_t)(regs->HW_CAP & 0x07U); in _i3c_dev_role_config_get()
1034 void _i3c_DAT_write(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx, in _i3c_DAT_write() argument
1039 entry_addr = (uint32_t *)((uint32_t)regs + ((uint32_t)DAT_start + ((uint32_t)DAT_idx * 4u))); in _i3c_DAT_write()
1052 uint32_t _i3c_DAT_read(struct mec_i3c_host_regs *regs, uint16_t DAT_start, uint8_t DAT_idx) in _i3c_DAT_read() argument
1057 entry_addr = (uint32_t *)((uint32_t)regs + ((uint32_t)DAT_start + ((uint32_t)DAT_idx * 4u))); in _i3c_DAT_read()
1072 void _i3c_DCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t DCT_idx, in _i3c_DCT_read() argument
1079 (uint32_t *)((uint32_t)regs + ((uint32_t)DCT_start + ((uint32_t)DCT_idx * 4u * 4u))); in _i3c_DCT_read()
1102 void _i3c_SDCT_read(struct mec_i3c_host_regs *regs, uint16_t DCT_start, uint8_t idx, in _i3c_SDCT_read() argument
1108 entry_addr = (uint32_t *)((uint32_t)regs + ((uint32_t)DCT_start + ((uint32_t)idx * 4u))); in _i3c_SDCT_read()
1125 void _i3c_fifo_write(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len) in _i3c_fifo_write() argument
1136 regs->TX_DATA = dword_ptr[i]; in _i3c_fifo_write()
1144 regs->TX_DATA = last_dword; in _i3c_fifo_write()
1155 void _i3c_fifo_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len) in _i3c_fifo_read() argument
1166 dword_ptr[i] = regs->RX_DATA; in _i3c_fifo_read()
1173 last_dword = regs->RX_DATA; in _i3c_fifo_read()
1185 void _i3c_ibi_data_read(struct mec_i3c_host_regs *regs, uint8_t *buffer, uint16_t len) in _i3c_ibi_data_read() argument
1201 drain_dword |= regs->IBI_QUE_STS; in _i3c_ibi_data_read()
1207 dword_ptr[i] = regs->IBI_QUE_STS; in _i3c_ibi_data_read()
1215 last_dword = regs->IBI_QUE_STS; in _i3c_ibi_data_read()
1227 void _i3c_xfers_reset(struct mec_i3c_host_regs *regs) in _i3c_xfers_reset() argument
1231 regs->RST_CTRL = RESET_CTRL_RX_FIFO_RST | RESET_CTRL_TX_FIFO_RST | in _i3c_xfers_reset()
1235 reg_val = regs->RST_CTRL; in _i3c_xfers_reset()
1244 void _i3c_tx_fifo_rst(struct mec_i3c_host_regs *regs) in _i3c_tx_fifo_rst() argument
1246 regs->RST_CTRL = RESET_CTRL_TX_FIFO_RST; in _i3c_tx_fifo_rst()
1254 void _i3c_rx_fifo_rst(struct mec_i3c_host_regs *regs) in _i3c_rx_fifo_rst() argument
1256 regs->RST_CTRL = RESET_CTRL_RX_FIFO_RST; in _i3c_rx_fifo_rst()
1264 void _i3c_cmd_queue_rst(struct mec_i3c_host_regs *regs) in _i3c_cmd_queue_rst() argument
1266 regs->RST_CTRL = RESET_CTRL_CMD_Q_RST; in _i3c_cmd_queue_rst()
1274 void _i3c_soft_reset(struct mec_i3c_host_regs *regs) in _i3c_soft_reset() argument
1278 regs->RST_CTRL = RESET_CTRL_SOFT_RST; in _i3c_soft_reset()
1281 reg_val = regs->RST_CTRL; in _i3c_soft_reset()
1290 void _i3c_command_write(struct mec_i3c_host_regs *regs, uint32_t cmd) in _i3c_command_write() argument
1292 regs->CMD = cmd; in _i3c_command_write()
1299 uint8_t _i3c_tx_fifo_depth_get(struct mec_i3c_host_regs *regs) in _i3c_tx_fifo_depth_get() argument
1301 …return (uint8_t)((FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(3, 0)) >> Q_CAP_TX_FI… in _i3c_tx_fifo_depth_get()
1308 uint8_t _i3c_rx_fifo_depth_get(struct mec_i3c_host_regs *regs) in _i3c_rx_fifo_depth_get() argument
1310 …return (uint8_t)((FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(7, 4)) >> Q_CAP_RX_FI… in _i3c_rx_fifo_depth_get()
1317 uint8_t _i3c_cmd_fifo_depth_get(struct mec_i3c_host_regs *regs) in _i3c_cmd_fifo_depth_get() argument
1319 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(11, 8)) >> Q_CAP_CMD_F… in _i3c_cmd_fifo_depth_get()
1326 uint8_t _i3c_resp_fifo_depth_get(struct mec_i3c_host_regs *regs) in _i3c_resp_fifo_depth_get() argument
1328 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(15, 12)) >> Q_CAP_RESP… in _i3c_resp_fifo_depth_get()
1335 uint8_t _i3c_ibi_fifo_depth_get(struct mec_i3c_host_regs *regs) in _i3c_ibi_fifo_depth_get() argument
1337 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(19, 16)) >> Q_CAP_IBI_… in _i3c_ibi_fifo_depth_get()
1343 void _i3c_tgt_pid_set(struct mec_i3c_sec_regs *regs, in _i3c_tgt_pid_set() argument
1350 regs->MIPI_MAN_ID = (tgt_mipi_mfg_id << TGT_MIPI_MFG_ID_BITPOS); in _i3c_tgt_pid_set()
1353 regs->NORM_PROV_ID = (tgt_part_id << TGT_PART_ID_BITPOS) | in _i3c_tgt_pid_set()
1363 bool _i3c_tgt_dyn_addr_valid_get(struct mec_i3c_sec_regs *regs) in _i3c_tgt_dyn_addr_valid_get() argument
1365 return (bool)(regs->DEV_ADDR & sbit_DEVICE_ADDR_DYNAMIC_ADDR_VALID); in _i3c_tgt_dyn_addr_valid_get()
1372 uint8_t _i3c_tgt_dyn_addr_get(struct mec_i3c_sec_regs *regs) in _i3c_tgt_dyn_addr_get() argument
1374 return (uint8_t)((regs->DEV_ADDR & MEC_GENMASK(22, 16)) >> DEVICE_ADDR_DYNAMIC_ADDR_BITPOS); in _i3c_tgt_dyn_addr_get()
1380 void _i3c_tgt_mrl_set(struct mec_i3c_sec_regs *regs, uint16_t mrl) in _i3c_tgt_mrl_set() argument
1382 regs->MAX_RW_LEN = (regs->MAX_RW_LEN & ~(MEC_GENMASK(31, 16))) | (mrl << MRL_BITPOS); in _i3c_tgt_mrl_set()
1388 void _i3c_tgt_mwl_set(struct mec_i3c_sec_regs *regs, uint16_t mwl) in _i3c_tgt_mwl_set() argument
1390 regs->MAX_RW_LEN = (regs->MAX_RW_LEN & ~(MEC_GENMASK(15, 0))) | (mwl << MWL_BITPOS); in _i3c_tgt_mwl_set()
1396 void _i3c_tgt_mxds_set(struct mec_i3c_sec_regs *regs, in _i3c_tgt_mxds_set() argument
1402 regs->MAX_DS = (wr_speed << MXDS_MAX_WR_SPEED_BITPOS) | in _i3c_tgt_mxds_set()
1405 regs->MAX_RD_TAR = MXDS_MAX_RD_TURN_MASK(rd_trnd_us); in _i3c_tgt_mxds_set()
1411 bool _i3c_tgt_SIR_enabled(struct mec_i3c_sec_regs *regs) in _i3c_tgt_SIR_enabled() argument
1414 if (regs->TGT_EVT_STS & TGT_EVT_STS_SIR_EN) { in _i3c_tgt_SIR_enabled()
1424 bool _i3c_tgt_MR_enabled(struct mec_i3c_sec_regs *regs) in _i3c_tgt_MR_enabled() argument
1427 if (regs->TGT_EVT_STS & TGT_EVT_STS_MIR_EN) { in _i3c_tgt_MR_enabled()
1437 void _i3c_tgt_raise_ibi_SIR(struct mec_i3c_sec_regs *regs, uint8_t *sir_data, uint8_t sir_datalen, in _i3c_tgt_raise_ibi_SIR() argument
1442 regs->TARG_IREQ = (mdb << TGT_INTR_REQ_MDB_BITPOS) | in _i3c_tgt_raise_ibi_SIR()
1450 regs->TARG_IREQ_DATA = sir_data_dword; in _i3c_tgt_raise_ibi_SIR()
1452 regs->TARG_IREQ |= TGT_INTR_REQ_SIR; in _i3c_tgt_raise_ibi_SIR()
1458 void _i3c_tgt_raise_ibi_MR(struct mec_i3c_sec_regs *regs) in _i3c_tgt_raise_ibi_MR() argument
1460 regs->TARG_IREQ = TGT_INTR_REQ_MR; in _i3c_tgt_raise_ibi_MR()
1463 regs->DEV_EXT_CTRL &= ~(DEV_REQMST_ACK_CTRL_NACK); in _i3c_tgt_raise_ibi_MR()
1469 bool _i3c_tgt_ibi_resp_get(struct mec_i3c_sec_regs *regs, uint8_t *sir_rem_datalen) in _i3c_tgt_ibi_resp_get() argument
1475 *sir_rem_datalen = (regs->TARG_IBI_RESP >> TGT_IBI_RESP_DATALEN_BITPOS) & 0xFF; in _i3c_tgt_ibi_resp_get()
1477 if (TGT_IBI_RESP_SUCCESS == (regs->TARG_IBI_RESP & 0x3)) { in _i3c_tgt_ibi_resp_get()
1487 void _i3c_tgt_MRL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_rd_len) in _i3c_tgt_MRL_get() argument
1489 *max_rd_len = (uint16_t)(regs->MAX_RW_LEN >> 16); in _i3c_tgt_MRL_get()
1495 void _i3c_tgt_MWL_get(struct mec_i3c_sec_regs *regs, uint16_t *max_wr_len) in _i3c_tgt_MWL_get() argument
1497 *max_wr_len = (uint16_t)(regs->MAX_RW_LEN & 0xFFFF); in _i3c_tgt_MWL_get()
1503 void _i3c_tgt_MRL_MWL_set(struct mec_i3c_sec_regs *regs, uint16_t max_rd_len, uint16_t max_wr_len) in _i3c_tgt_MRL_MWL_set() argument
1505 regs->MAX_RW_LEN = ((uint32_t)max_rd_len << 16) | max_wr_len; in _i3c_tgt_MRL_MWL_set()
1511 void _i3c_tgt_MWL_set(struct mec_i3c_sec_regs *regs, uint16_t *max_wr_len) in _i3c_tgt_MWL_set() argument
1513 *max_wr_len = (uint16_t)(regs->MAX_RW_LEN & 0xFFFFu); in _i3c_tgt_MWL_set()
1519 bool _i3c_tgt_MRL_updated(struct mec_i3c_sec_regs *regs) in _i3c_tgt_MRL_updated() argument
1523 if (regs->TGT_EVT_STS & TGT_EVT_STS_MRL_UPDATED) { in _i3c_tgt_MRL_updated()
1526 regs->TGT_EVT_STS = TGT_EVT_STS_MRL_UPDATED; in _i3c_tgt_MRL_updated()
1535 bool _i3c_tgt_MWL_updated(struct mec_i3c_sec_regs *regs) in _i3c_tgt_MWL_updated() argument
1539 if (regs->TGT_EVT_STS & TGT_EVT_STS_MWL_UPDATED) { in _i3c_tgt_MWL_updated()
1542 regs->TGT_EVT_STS = TGT_EVT_STS_MWL_UPDATED; in _i3c_tgt_MWL_updated()
1551 void _i3c_tgt_max_speed_update(struct mec_i3c_sec_regs *regs, uint8_t max_rd_speed, in _i3c_tgt_max_speed_update() argument
1554 regs->MAX_DS &= (uint32_t)~(TGT_MAX_WR_DATA_SPEED_MASK << TGT_MAX_WR_DATA_SPEED_POS); in _i3c_tgt_max_speed_update()
1555 regs->MAX_DS &= (uint32_t)~(TGT_MAX_RD_DATA_SPEED_MASK << TGT_MAX_RD_DATA_SPEED_POS); in _i3c_tgt_max_speed_update()
1557 regs->MAX_DS |= (max_wr_speed << TGT_MAX_WR_DATA_SPEED_POS); in _i3c_tgt_max_speed_update()
1558 regs->MAX_DS |= (max_rd_speed << TGT_MAX_RD_DATA_SPEED_POS); in _i3c_tgt_max_speed_update()
1564 void _i3c_tgt_clk_to_data_turn_update(struct mec_i3c_sec_regs *regs, uint8_t clk_data_turn_time) in _i3c_tgt_clk_to_data_turn_update() argument
1566 regs->MAX_DS &= (uint32_t)~(TGT_CLK_TO_DATA_TURN_MASK << TGT_CLK_TO_DATA_TURN_POS); in _i3c_tgt_clk_to_data_turn_update()
1568 regs->MAX_DS |= ((uint32_t)clk_data_turn_time << TGT_CLK_TO_DATA_TURN_POS); in _i3c_tgt_clk_to_data_turn_update()