| /Zephyr-latest/boards/st/stm32n6570_dk/ |
| D | stm32n6570_dk_common.dtsi | 78 clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
83 clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
88 &rcc {
100 clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
101 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
109 clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
110 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
117 clocks = <&rcc STM32_CLOCK(APB1, 21)>,
118 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
126 clocks = <&rcc STM32_CLOCK(APB4, 7)>,
[all …]
|
| /Zephyr-latest/boards/st/nucleo_n657x0_q/ |
| D | nucleo_n657x0_q_common.dtsi | 96 clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
101 clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
106 &rcc {
118 clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
119 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
127 clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
128 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
135 clocks = <&rcc STM32_CLOCK(APB1, 21)>,
136 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
144 clocks = <&rcc STM32_CLOCK(APB4, 7)>,
[all …]
|
| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l4p5.dtsi | 44 rcc: rcc@40021000 { label
49 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
50 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
61 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
69 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
77 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
85 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
93 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
100 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
109 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
[all …]
|
| D | stm32l496.dtsi | 24 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
34 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
49 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN
64 clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
65 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
69 clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
70 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
| D | stm32l431.dtsi | 28 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
45 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
53 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
83 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
[all …]
|
| D | stm32l451.dtsi | 29 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
37 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
42 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
43 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
64 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
85 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
93 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
[all …]
|
| D | stm32l471.dtsi | 20 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
28 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
81 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
[all …]
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 31 &rcc {
59 &rcc {
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
69 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
75 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
81 <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
|
| D | f4_sdmmc48_pll.overlay | 10 /* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/
11 clocks = <&rcc STM32_SRC_PLLI2S_Q CK48M_SEL(1)>;
25 clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
27 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
28 /* <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; */
|
| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 39 &rcc {
73 &rcc {
85 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
86 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
93 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
94 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
99 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
100 <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;
|
| /Zephyr-latest/dts/arm/st/mp1/ |
| D | stm32mp157.dtsi | 45 rcc: rcc@50000000 { label
46 compatible = "st,stm32mp1-rcc";
51 compatible = "st,stm32-rcc-rctl";
89 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
97 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
105 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
113 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
121 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
129 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
137 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
[all …]
|
| /Zephyr-latest/dts/arm/st/f7/ |
| D | stm32f765.dtsi | 37 clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
45 clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
66 clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
77 clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
78 <&rcc STM32_CLOCK(AHB1, 26U)>,
79 <&rcc STM32_CLOCK(AHB1, 27U)>,
80 <&rcc STM32_CLOCK(AHB1, 28U)>;
87 clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
88 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
|
| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h7.dtsi | 153 rcc: rcc@58024400 { label
154 compatible = "st,stm32h7-rcc";
159 compatible = "st,stm32-rcc-rctl";
190 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
198 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
206 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
214 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
222 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
230 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
238 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
[all …]
|
| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h5.dtsi | 144 clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
149 rcc: rcc@44020c00 { label
150 compatible = "st,stm32u5-rcc";
156 compatible = "st,stm32-rcc-rctl";
193 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
201 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
209 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
217 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
225 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
231 clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
[all …]
|
| D | stm32h562.dtsi | 32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
138 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
[all …]
|
| /Zephyr-latest/dts/arm/st/u0/ |
| D | stm32u0.dtsi | 112 rcc: rcc@40021000 { label
113 compatible = "st,stm32f0-rcc";
119 compatible = "st,stm32-rcc-rctl";
147 clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
155 clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
163 clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
171 clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
179 clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
187 clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
194 clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
[all …]
|
| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f405.dtsi | 26 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
34 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
42 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
49 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
67 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
131 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
[all …]
|
| D | stm32f412.dtsi | 23 clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
39 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
47 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
75 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
85 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
112 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
135 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
[all …]
|
| D | stm32f446.dtsi | 26 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
37 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
46 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
66 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
76 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
83 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
84 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
96 clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
97 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
[all …]
|
| D | stm32f469.dtsi | 14 clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
15 <&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>;
20 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
21 <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>;
|
| /Zephyr-latest/samples/boards/st/mco/boards/ |
| D | nucleo_f446ze.overlay | 14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
|
| /Zephyr-latest/dts/riscv/wch/ch32v208/ |
| D | ch32v208.dtsi | 80 clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
89 clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
98 clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
107 clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
114 clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
123 clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
132 clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
141 clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
147 rcc: rcc@40021000 { label
148 compatible = "wch,rcc";
|
| /Zephyr-latest/boards/st/nucleo_u083rc/ |
| D | nucleo_u083rc.dts | 95 &rcc {
119 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
120 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
149 clocks = <&rcc STM32_CLOCK(APB1, 31U)>,
150 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
170 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>,
171 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
180 clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
181 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
188 clocks = <&rcc STM32_CLOCK(APB1, 10U)>,
[all …]
|
| /Zephyr-latest/dts/arm/st/f2/ |
| D | stm32f2.dtsi | 95 rcc: rcc@40023800 { label
96 compatible = "st,stm32-rcc";
101 compatible = "st,stm32-rcc-rctl";
132 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
140 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
148 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
156 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
164 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
172 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
180 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
[all …]
|
| /Zephyr-latest/dts/arm/st/n6/ |
| D | stm32n6.dtsi | 232 rcc: rcc@56028000 { label
233 compatible = "st,stm32n6-rcc";
239 compatible = "st,stm32-rcc-rctl";
276 clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
284 clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
292 clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
300 clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
308 clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
316 clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
324 clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
[all …]
|
