1/*
2 * Copyright (c) 2023 SILA Embedded Solutions GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l4.dtsi>
8
9/ {
10
11	clocks {
12		clk_hsi48: clk-hsi48 {
13			#clock-cells = <0>;
14			compatible = "fixed-clock";
15			clock-frequency = <DT_FREQ_M(48)>;
16			status = "disabled";
17		};
18	};
19
20	soc {
21		compatible = "st,stm32l451", "st,stm32l4", "simple-bus";
22
23		pinctrl: pin-controller@48000000 {
24			gpiod: gpio@48000c00 {
25				compatible = "st,stm32-gpio";
26				gpio-controller;
27				#gpio-cells = <2>;
28				reg = <0x48000c00 0x400>;
29				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
30			};
31
32			gpioe: gpio@48001000 {
33				compatible = "st,stm32-gpio";
34				gpio-controller;
35				#gpio-cells = <2>;
36				reg = <0x48001000 0x400>;
37				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
38			};
39		};
40
41		rng: rng@50060800 {
42			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
43				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
44		};
45
46		i2c2: i2c@40005800 {
47			compatible = "st,stm32-i2c-v2";
48			clock-frequency = <I2C_BITRATE_STANDARD>;
49			#address-cells = <1>;
50			#size-cells = <0>;
51			reg = <0x40005800 0x400>;
52			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
53			interrupts = <33 0>, <34 0>;
54			interrupt-names = "event", "error";
55			status = "disabled";
56		};
57
58		i2c4: i2c@40008400 {
59			compatible = "st,stm32-i2c-v2";
60			clock-frequency = <I2C_BITRATE_STANDARD>;
61			#address-cells = <1>;
62			#size-cells = <0>;
63			reg = <0x40008400 0x400>;
64			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
65			interrupts = <83 0>, <84 0>;
66			interrupt-names = "event", "error";
67			status = "disabled";
68		};
69
70		spi2: spi@40003800 {
71			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
72			#address-cells = <1>;
73			#size-cells = <0>;
74			reg = <0x40003800 0x400>;
75			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
76			interrupts = <36 5>;
77			status = "disabled";
78		};
79
80		spi3: spi@40003c00 {
81			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
82			#address-cells = <1>;
83			#size-cells = <0>;
84			reg = <0x40003c00 0x400>;
85			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
86			interrupts = <51 5>;
87			status = "disabled";
88		};
89
90		usart3: serial@40004800 {
91			compatible = "st,stm32-usart", "st,stm32-uart";
92			reg = <0x40004800 0x400>;
93			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
94			resets = <&rctl STM32_RESET(APB1L, 18U)>;
95			interrupts = <39 0>;
96			status = "disabled";
97		};
98
99		uart4: serial@40004c00 {
100			compatible = "st,stm32-uart";
101			reg = <0x40004c00 0x400>;
102			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
103			resets = <&rctl STM32_RESET(APB1L, 19U)>;
104			interrupts = <52 0>;
105			status = "disabled";
106		};
107
108		timers3: timers@40000400 {
109			compatible = "st,stm32-timers";
110			reg = <0x40000400 0x400>;
111			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
112			resets = <&rctl STM32_RESET(APB1L, 1U)>;
113			interrupts = <29 0>;
114			interrupt-names = "global";
115			st,prescaler = <0>;
116			status = "disabled";
117
118			pwm {
119				compatible = "st,stm32-pwm";
120				status = "disabled";
121				#pwm-cells = <3>;
122			};
123
124			counter {
125				compatible = "st,stm32-counter";
126				status = "disabled";
127			};
128		};
129
130		dac1: dac@40007400 {
131			compatible = "st,stm32-dac";
132			reg = <0x40007400 0x400>;
133			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
134			status = "disabled";
135			#io-channel-cells = <1>;
136		};
137
138		can1: can@40006400 {
139			compatible = "st,stm32-bxcan";
140			reg = <0x40006400 0x400>;
141			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
142			interrupt-names = "TX", "RX0", "RX1", "SCE";
143			clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
144			status = "disabled";
145		};
146
147		sdmmc1: sdmmc@40012800 {
148			compatible = "st,stm32-sdmmc";
149			reg = <0x40012800 0x400>;
150			clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
151				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
152			resets = <&rctl STM32_RESET(APB2, 10U)>;
153			interrupts = <49 0>;
154			status = "disabled";
155		};
156
157		rtc@40002800 {
158			bbram: backup_regs {
159				compatible = "st,stm32-bbram";
160				st,backup-regs = <32>;
161				status = "disabled";
162			};
163		};
164	};
165
166	smbus2: smbus2 {
167		compatible = "st,stm32-smbus";
168		#address-cells = <1>;
169		#size-cells = <0>;
170		i2c = <&i2c2>;
171		status = "disabled";
172	};
173
174	smbus4: smbus4 {
175		compatible = "st,stm32-smbus";
176		#address-cells = <1>;
177		#size-cells = <0>;
178		i2c = <&i2c4>;
179		status = "disabled";
180	};
181};
182