1/*
2 * Copyright (c) 2017 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l475.dtsi>
8
9/ {
10
11	clocks {
12		clk_hsi48: clk-hsi48 {
13			#clock-cells = <0>;
14			compatible = "fixed-clock";
15			clock-frequency = <DT_FREQ_M(48)>;
16			status = "disabled";
17		};
18	};
19
20	soc {
21		compatible = "st,stm32l496", "st,stm32l4", "simple-bus";
22
23		rng: rng@50060800 {
24			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
25				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
26		};
27
28		i2c4: i2c@40008400 {
29			compatible = "st,stm32-i2c-v2";
30			clock-frequency = <I2C_BITRATE_STANDARD>;
31			#address-cells = <1>;
32			#size-cells = <0>;
33			reg = <0x40008400 0x400>;
34			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
35			interrupts = <83 0>, <84 0>;
36			interrupt-names = "event", "error";
37			status = "disabled";
38		};
39
40		pinctrl: pin-controller@48000000 {
41			reg = <0x48000000 0x2400>;
42
43			gpioi: gpio@48002000 {
44				compatible = "st,stm32-gpio";
45				gpio-controller;
46				#gpio-cells = <2>;
47				ngpios = <12>;
48				reg = <0x48002000 0x400>;
49				clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
50			};
51		};
52
53		can2: can@40006800 {
54			compatible = "st,stm32-bxcan";
55			reg = <0x40006800 0x400>;
56			interrupts = <86 0>, <87 0>, <88 0>, <89 0>;
57			interrupt-names = "TX", "RX0", "RX1", "SCE";
58			clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN
59			master-can-reg = <0x40006400>;
60			status = "disabled";
61		};
62
63		usbotg_fs: otgfs@50000000 {
64			clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
65				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
66		};
67
68		sdmmc1: sdmmc@40012800 {
69			clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
70				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
71		};
72	};
73
74	die_temp: dietemp {
75		ts-cal2-temp = <130>;
76	};
77
78	smbus4: smbus4 {
79		compatible = "st,stm32-smbus";
80		#address-cells = <1>;
81		#size-cells = <0>;
82		i2c = <&i2c4>;
83		status = "disabled";
84	};
85};
86