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/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
46 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dsystem_clocks.dtsi13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <48000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <8000000>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <96000000>;
37 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_clk.dtsi9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
27 #clock-cells = <0>;
[all …]
Djh7110-clk.dtsi10 #clock-cells = <0>;
11 compatible = "fixed-clock";
12 clock-frequency = <125000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-frequency = <100000000>;
/Zephyr-latest/dts/arm/silabs/
Defr32xg23.dtsi11 #include <dt-bindings/clock/silabs/xg23-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
41 clock-div = <1>;
[all …]
Defr32mg24.dtsi11 #include <dt-bindings/clock/silabs/xg24-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
41 clock-div = <1>;
[all …]
Defr32mg21.dtsi11 #include <dt-bindings/clock/silabs/xg21-clock.h>
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
31 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "fixed-factor-clock";
38 clock-div = <2>;
41 #clock-cells = <0>;
[all …]
Defr32bg2x.dtsi22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
31 clock-div = <1>;
34 #clock-cells = <0>;
35 compatible = "fixed-factor-clock";
38 clock-div = <2>;
41 #clock-cells = <0>;
42 compatible = "fixed-factor-clock";
[all …]
Defr32bg27.dtsi8 #include <dt-bindings/clock/silabs/xg27-clock.h>
14 #clock-cells = <0>;
15 compatible = "fixed-factor-clock";
19 #clock-cells = <0>;
20 compatible = "fixed-factor-clock";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
35 clock-frequency = <DT_FREQ_M(38)>;
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
48 compatible = "raspberrypi,pico-clock";
50 clock-names = "pll_sys";
51 clock-frequency = <125000000>;
52 #clock-cells = <0>;
57 compatible = "raspberrypi,pico-clock";
59 clock-names = "pll_sys";
60 clock-frequency = <125000000>;
61 #clock-cells = <0>;
65 compatible = "raspberrypi,pico-clock";
[all …]
Drp2350.dtsi9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
44 compatible = "raspberrypi,pico-clock";
46 clock-names = "pll_sys";
47 clock-frequency = <150000000>;
48 #clock-cells = <0>;
53 compatible = "raspberrypi,pico-clock";
55 clock-names = "pll_sys";
56 clock-frequency = <150000000>;
57 #clock-cells = <0>;
61 compatible = "raspberrypi,pico-clock";
[all …]
/Zephyr-latest/boards/infineon/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts92 /* System clock configuration */
95 clock-frequency = <100000000>;
99 clock-div = <1>;
103 /* CM4 core clock = 100MHz
104 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
107 clock-div = <1>;
110 /* CM0+ core clock = 50MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
114 clock-div = <2>;
117 /* PERI core clock = 100MHz
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dcy8ckit_062s2_ai.dts53 clock-frequency = <100000000>;
57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
62 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
65 clock-div = <1>;
68 /* CM0+ core clock = 50MHz
69 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
72 clock-div = <2>;
75 /* PERI core clock = 100MHz
76 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
24 clock-frequency = <DT_FREQ_M(48)>;
25 #clock-cells = <0>;
28 moco: clock-moco {
[all …]
Dr7fa8m1xh.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
24 clock-frequency = <DT_FREQ_M(48)>;
25 #clock-cells = <0>;
28 moco: clock-moco {
[all …]
Dr7fa8d1xh.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
45 xtal: clock-main-osc {
46 compatible = "renesas,ra-cgc-external-clock";
47 clock-frequency = <DT_FREQ_M(20)>;
48 #clock-cells = <0>;
52 hoco: clock-hoco {
53 compatible = "fixed-clock";
54 clock-frequency = <DT_FREQ_M(48)>;
55 #clock-cells = <0>;
58 moco: clock-moco {
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4w1ad2cng.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
73 xtal: clock-main-osc {
74 compatible = "renesas,ra-cgc-external-clock";
75 clock-frequency = <DT_FREQ_M(8)>;
76 #clock-cells = <0>;
80 hoco: clock-hoco {
81 compatible = "fixed-clock";
82 clock-frequency = <DT_FREQ_M(48)>;
83 #clock-cells = <0>;
86 moco: clock-moco {
[all …]
Dr7fa4e2b93cfm.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
65 clock-names = "opclk", "ramclk";
75 clock-names = "dllclk";
90 xtal: clock-main-osc {
91 compatible = "renesas,ra-cgc-external-clock";
92 clock-frequency = <DT_FREQ_M(20)>;
93 #clock-cells = <0>;
97 hoco: clock-hoco {
98 compatible = "fixed-clock";
99 clock-frequency = <DT_FREQ_M(20)>;
[all …]
/Zephyr-latest/drivers/timer/
DKconfig.nrf_xrtc14 System clock source is initiated but does not wait for clock readiness.
15 When this option is picked, system clock may not be ready when code relying
22 System clock source initialization waits until clock is available. In some
23 systems, clock initially runs from less accurate source which has faster
24 startup time and then seamlessly switches to the target clock source when
25 it is ready. When this option is picked, system clock is available after
26 system clock driver initialization but it may be less accurate. Option is
27 equivalent to waiting for stability if clock source does not have
33 System clock source initialization waits until clock is stable. When this
34 option is picked, system clock is available and stable after system clock
/Zephyr-latest/dts/arm/adi/max32/
Dmax32xxx.dtsi9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <DT_FREQ_M(100)>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <DT_FREQ_M(60)>;
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <DT_FREQ_K(8)>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi7 #include <zephyr/dt-bindings/clock/ra_clock.h>
48 xtal: clock-main-osc {
49 compatible = "renesas,ra-cgc-external-clock";
50 clock-frequency = <DT_FREQ_M(12)>;
51 #clock-cells = <0>;
55 hoco: clock-hoco {
56 compatible = "fixed-clock";
57 clock-frequency = <DT_FREQ_M(20)>;
58 #clock-cells = <0>;
61 moco: clock-moco {
[all …]
Dr7fa6e2bx.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
54 clock-names = "opclk", "ramclk";
64 clock-names = "dllclk";
99 xtal: clock-main-osc {
100 compatible = "renesas,ra-cgc-external-clock";
101 clock-frequency = <DT_FREQ_M(20)>;
102 #clock-cells = <0>;
106 hoco: clock-hoco {
107 compatible = "fixed-clock";
108 clock-frequency = <DT_FREQ_M(20)>;
[all …]
Dr7fa6m2ax.dtsi8 #include <zephyr/dt-bindings/clock/ra_clock.h>
92 xtal: clock-main-osc {
93 compatible = "renesas,ra-cgc-external-clock";
94 clock-frequency = <DT_FREQ_M(12)>;
95 #clock-cells = <0>;
99 hoco: clock-hoco {
100 compatible = "fixed-clock";
101 clock-frequency = <DT_FREQ_M(20)>;
102 #clock-cells = <0>;
105 moco: clock-moco {
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig35 int "Freescale K8x core clock divider"
38 This option specifies the divide value for the K8x processor core clock
39 from the system clock.
42 int "Freescale K8x bus clock divider"
45 This option specifies the divide value for the K8x bus clock from the
46 system clock.
49 int "Freescale K8x FlexBus clock divider"
52 This option specifies the divide value for the K8x FlexBus clock from the
53 system clock.
56 int "Freescale K8x flash clock divider"
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_ke1xf.dtsi9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
130 #clock-cells = <1>;
133 compatible = "fixed-clock";
135 #clock-cells = <0>;
139 compatible = "fixed-clock";
140 clock-frequency = <8000000>;
141 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 clock-frequency = <48000000>;
[all …]

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