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/Zephyr-latest/drivers/tee/optee/
Doptee_msg.h12 #define U(v) v ## U macro
23 #define OPTEE_MSG_ATTR_TYPE_NONE U(0x0)
24 #define OPTEE_MSG_ATTR_TYPE_VALUE_INPUT U(0x1)
25 #define OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT U(0x2)
26 #define OPTEE_MSG_ATTR_TYPE_VALUE_INOUT U(0x3)
27 #define OPTEE_MSG_ATTR_TYPE_RMEM_INPUT U(0x5)
28 #define OPTEE_MSG_ATTR_TYPE_RMEM_OUTPUT U(0x6)
29 #define OPTEE_MSG_ATTR_TYPE_RMEM_INOUT U(0x7)
33 #define OPTEE_MSG_ATTR_TYPE_TMEM_INPUT U(0x9)
34 #define OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT U(0xa)
[all …]
Doptee_smc.h20 #define OPTEE_SMC_32 U(0)
21 #define OPTEE_SMC_64 U(0x40000000)
22 #define OPTEE_SMC_FAST_CALL U(0x80000000)
23 #define OPTEE_SMC_STD_CALL U(0)
25 #define OPTEE_SMC_OWNER_MASK U(0x3F)
26 #define OPTEE_SMC_OWNER_SHIFT U(24)
28 #define OPTEE_SMC_FUNC_MASK U(0xFFFF)
49 #define OPTEE_SMC_OWNER_ARCH U(0)
50 #define OPTEE_SMC_OWNER_CPU U(1)
51 #define OPTEE_SMC_OWNER_SIP U(2)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dstm32f1-afio.h11 #define STM32_REMAP_REG_SHIFT 0U
76 #define STM32_AFIO_MAPR 0U
83 #define SPI1_REMAP0 STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR)
85 #define SPI1_REMAP1 STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR)
88 #define I2C1_REMAP0 STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR)
93 #define USART1_REMAP0 STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR)
98 #define USART2_REMAP0 STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR)
103 #define USART3_REMAP0 STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR)
110 #define TIM1_REMAP0 STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR)
117 #define TIM2_REMAP0 STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR)
[all …]
Dti-cc32xx-pinctrl.h34 #define TI_CC32XX_MUX_POS 0U
53 #define GPIO10_P1 TI_CC32XX_PINMUX(1U, 0U)
60 #define GPIO11_P2 TI_CC32XX_PINMUX(2U, 0U)
69 #define GPIO12_P3 TI_CC32XX_PINMUX(3U, 0U)
76 #define GPIO13_P4 TI_CC32XX_PINMUX(4U, 0U)
82 #define GPIO14_P5 TI_CC32XX_PINMUX(5U, 0U)
88 #define GPIO15_P6 TI_CC32XX_PINMUX(6U, 0U)
95 #define GPIO16_P7 TI_CC32XX_PINMUX(7U, 0U)
102 #define GPIO17_P8 TI_CC32XX_PINMUX(8U, 0U)
108 #define GPIO22_P15 TI_CC32XX_PINMUX(15U, 0U)
[all …]
/Zephyr-latest/soc/st/stm32/common/
Dstm32_hsem.h64 #define CFG_HW_RNG_SEMID 0U
85 #define CFG_HW_GPIO_SEMID 0U
92 #define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 0U
93 #define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 0U
94 #define CFG_HW_CLK48_CONFIG_SEMID 0U
95 #define CFG_HW_RCC_CRRCR_CCIPR_SEMID 0U
96 #define CFG_HW_ENTRY_STOP_MODE_SEMID 0U
97 #define CFG_HW_RCC_SEMID 0U
98 #define CFG_HW_FLASH_SEMID 0U
99 #define CFG_HW_PKA_SEMID 0U
[all …]
/Zephyr-latest/samples/subsys/portability/cmsis_rtos_v2/philosophers/src/
Dphil_obj_abstract.h37 {"sema0", 0, NULL, 0U},
38 {"sema1", 0, NULL, 0U},
39 {"sema2", 0, NULL, 0U},
40 {"sema3", 0, NULL, 0U},
41 {"sema4", 0, NULL, 0U},
42 {"sema5", 0, NULL, 0U}
53 {"Mutex0", osMutexRecursive | osMutexPrioInherit, NULL, 0U},
54 {"Mutex1", osMutexRecursive | osMutexPrioInherit, NULL, 0U},
55 {"Mutex2", osMutexRecursive | osMutexPrioInherit, NULL, 0U},
56 {"Mutex3", osMutexRecursive | osMutexPrioInherit, NULL, 0U},
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_gd32.c28 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U,
32 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
36 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
135 for (size_t i = 0U; i < ARRAY_SIZE(timer_ids); i++) { in clock_control_gd32_get_rate()
155 if ((cfg1 & RCU_CFG1_TIMERSEL_MSK) == 0U) { in clock_control_gd32_get_rate()
/Zephyr-latest/dts/arm/st/f4/
Dstm32f413.dtsi16 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
17 resets = <&rctl STM32_RESET(APB1, 19U)>;
25 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
34 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
43 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
52 clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
[all …]
Dstm32f405.dtsi26 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
34 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
42 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
49 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
50 resets = <&rctl STM32_RESET(APB1, 18U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
67 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
[all …]
Dstm32f412.dtsi39 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
47 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
55 resets = <&rctl STM32_RESET(APB1, 18U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
75 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
85 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
97 resets = <&rctl STM32_RESET(APB1, 5U)>;
112 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
130 resets = <&rctl STM32_RESET(APB1L, 19U)>;
[all …]
/Zephyr-latest/lib/utils/
Drb.c19 enum rb_color { RED = 0U, BLACK = 1U };
24 if (side != 0U) { in get_child()
37 if (side != 0U) { in set_child()
88 uint8_t side = tree->lessthan_fn(node, stack[sz - 1]) ? 0U : 1U; in find_and_stack()
115 CHECK(get_child(parent, 0U) == child || get_child(parent, 1U) == child); in get_side()
117 return (get_child(parent, 1U) == child) ? 1U : 0U; in get_side()
138 struct rbnode *b = get_child(child, (side == 0U) ? 1U : 0U); in rotate()
147 set_child(child, (side == 0U) ? 1U : 0U, parent); in rotate()
164 CHECK((get_child(node, 0U) == NULL) || in fix_extra_red()
165 is_black(get_child(node, 0U))); in fix_extra_red()
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l471.dtsi20 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
28 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
[all …]
Dstm32l4p5.dtsi49 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
61 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
69 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
77 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
85 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
93 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
100 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
101 resets = <&rctl STM32_RESET(APB1L, 18U)>;
109 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
110 resets = <&rctl STM32_RESET(APB1L, 19U)>;
[all …]
Dstm32l431.dtsi28 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
53 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
83 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
84 resets = <&rctl STM32_RESET(APB1L, 18U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
93 resets = <&rctl STM32_RESET(APB1L, 5U)>;
[all …]
/Zephyr-latest/tests/bluetooth/controller/ctrl_tx_queue/src/
Dmain.c37 zassert_equal(0U, tx_q.pause_data, "pause_data must be zero on init"); in ZTEST()
58 for (int i = 0U; i < SIZE; i++) { in ZTEST()
63 for (int i = 0U; i < SIZE; i++) { in ZTEST()
87 for (int i = 0U; i < SIZE; i++) { in ZTEST()
92 for (int i = 0U; i < SIZE; i++) { in ZTEST()
117 for (int i = 0U; i < SIZE; i++) { in ZTEST()
123 for (int i = 0U; i < SIZE; i++) { in ZTEST()
154 for (int i = 0U; i < SIZE; i++) { in ZTEST()
163 for (int i = 0U; i < SIZE; i++) { in ZTEST()
168 for (int i = 0U; i < SIZE; i++) { in ZTEST()
[all …]
/Zephyr-latest/tests/subsys/pm/policy_api/src/
Dmain.c36 next = pm_policy_next_state(0U, 0); in ZTEST()
39 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(10999)); in ZTEST()
42 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(110000)); in ZTEST()
47 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(1099999)); in ZTEST()
50 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(1100000)); in ZTEST()
55 next = pm_policy_next_state(0U, K_TICKS_FOREVER); in ZTEST()
89 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(110000)); in ZTEST()
100 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(110000)); in ZTEST()
111 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(110000)); in ZTEST()
120 next = pm_policy_next_state(0U, k_us_to_ticks_floor32(110000)); in ZTEST()
[all …]
/Zephyr-latest/tests/benchmarks/latency_measure/src/
Dheap_malloc_free.c16 timing_t heap_malloc_start_time = 0U; in heap_malloc_free()
17 timing_t heap_malloc_end_time = 0U; in heap_malloc_free()
19 timing_t heap_free_start_time = 0U; in heap_malloc_free()
20 timing_t heap_free_end_time = 0U; in heap_malloc_free()
22 uint32_t count = 0U; in heap_malloc_free()
23 uint32_t sum_malloc = 0U; in heap_malloc_free()
24 uint32_t sum_free = 0U; in heap_malloc_free()
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xc.dtsi29 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
30 resets = <&rctl STM32_RESET(APB1, 19U)>;
38 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
47 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
64 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
[all …]
/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi89 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
97 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
105 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
113 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
121 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
129 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
137 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
145 clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
153 clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
161 clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
[all …]
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi19 clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
29 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
41 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
61 resets = <&rctl STM32_RESET(APB1, 1U)>;
82 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
98 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
[all …]
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi132 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
140 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
148 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
156 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
164 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
172 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
180 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
188 clocks = <&rcc STM32_CLOCK(AHB1, 7U)>;
196 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
203 clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-npm1300-gpio.h37 #define NPM1300_GPIO_DRIVE_1MA (0U << 8U)
55 #define NPM1300_GPIO_DEBOUNCE_OFF (0U << 9U)
73 #define NPM1300_GPIO_WDT_RESET_OFF (0U << 10U)
91 #define NPM1300_GPIO_PWRLOSSWARN_OFF (0U << 11U)
/Zephyr-latest/drivers/gpio/
Dgpio_npm2100.c64 if ((mask & BIT(idx)) != 0U) { in gpio_npm2100_port_set_masked_raw()
67 if (ret != 0U) { in gpio_npm2100_port_set_masked_raw()
83 return gpio_npm2100_port_set_masked_raw(dev, pins, 0U); in gpio_npm2100_port_clear_bits_raw()
90 uint8_t reg = 0U; in gpio_npm2100_configure()
101 if ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0U) { in gpio_npm2100_configure()
110 if ((flags & GPIO_INPUT) != 0U) { in gpio_npm2100_configure()
113 if ((flags & GPIO_OUTPUT) != 0U) { in gpio_npm2100_configure()
116 if ((flags & GPIO_SINGLE_ENDED) != 0U) { in gpio_npm2100_configure()
119 if ((flags & GPIO_PULL_UP) != 0U) { in gpio_npm2100_configure()
122 if ((flags & GPIO_PULL_DOWN) != 0U) { in gpio_npm2100_configure()
[all …]
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dnuclei_csr.h32 #define MCOUNTINHIBIT_CY BIT(0U)
38 #define MILM_CTL_ILM_EN BIT(0U)
44 #define MDLM_CTL_DLM_EN BIT(0U)
55 #define MCACHE_CTL_IC_EN BIT(0U)
67 #define MTVT2_MTVT2EN BIT(0U)
70 #define MCFG_INFO_TEE BIT(0U)
82 #define MICFG_IC_SET (0xFU << 0U)
90 #define MDCFG_DC_SET (0xFU << 0U)
109 #define CCM_SUEN_SUEN (0x1U << 0U)
110 #define CCM_DATA_DATA (0x7U << 0U)
[all …]

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