Lines Matching refs:U
20 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
28 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
81 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
110 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
111 resets = <&rctl STM32_RESET(APB1L, 1U)>;
132 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
133 resets = <&rctl STM32_RESET(APB1L, 2U)>;
154 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
155 resets = <&rctl STM32_RESET(APB1L, 3U)>;
176 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
177 resets = <&rctl STM32_RESET(APB1L, 5U)>;
192 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
193 resets = <&rctl STM32_RESET(APB2, 13U)>;
209 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
210 resets = <&rctl STM32_RESET(APB2, 18U)>;
233 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
240 clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
242 resets = <&rctl STM32_RESET(APB2, 10U)>;
250 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
258 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;