Lines Matching refs:U
32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
130 resets = <&rctl STM32_RESET(APB1L, 19U)>;
138 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
139 resets = <&rctl STM32_RESET(APB1L, 20U)>;
147 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
148 resets = <&rctl STM32_RESET(APB1L, 30U)>;
156 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
157 resets = <&rctl STM32_RESET(APB1L, 31U)>;
165 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
166 resets = <&rctl STM32_RESET(APB1H, 0U)>;
174 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
175 resets = <&rctl STM32_RESET(APB1L, 25U)>;
183 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
184 resets = <&rctl STM32_RESET(APB1L, 26U)>;
192 clocks = <&rcc STM32_CLOCK(APB1, 27U)>;
193 resets = <&rctl STM32_RESET(APB1L, 27U)>;
201 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
202 resets = <&rctl STM32_RESET(APB1H, 1U)>;
213 clocks = <&rcc STM32_CLOCK(APB3, 7U)>;
225 clocks = <&rcc STM32_CLOCK(APB3, 8U)>;
237 clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
247 clocks = <&rcc STM32_CLOCK(APB3, 5U)>;
257 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
266 clocks = <&rcc STM32_CLOCK(AHB4, 20U)>,
276 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
293 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
294 resets = <&rctl STM32_RESET(APB1L, 2U)>;
314 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
315 resets = <&rctl STM32_RESET(APB1L, 3U)>;
335 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
336 resets = <&rctl STM32_RESET(APB1L, 6U)>;
356 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
357 resets = <&rctl STM32_RESET(APB1L, 7U)>;
377 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
378 resets = <&rctl STM32_RESET(APB1L, 8U)>;
398 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
399 resets = <&rctl STM32_RESET(APB2, 16U)>;
419 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
420 resets = <&rctl STM32_RESET(APB2, 17U)>;
440 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
441 resets = <&rctl STM32_RESET(APB2, 18U)>;
461 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
462 resets = <&rctl STM32_RESET(AHB2, 16U)>;
474 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
482 clocks = <&rcc STM32_CLOCK(AHB4, 11U)>,
484 resets = <&rctl STM32_RESET(AHB4, 11U)>;
492 clocks = <&rcc STM32_CLOCK(AHB4, 16U)>;