Lines Matching refs:U
49 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
61 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
69 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
77 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
85 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
93 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
100 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
101 resets = <&rctl STM32_RESET(APB1L, 18U)>;
109 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
110 resets = <&rctl STM32_RESET(APB1L, 19U)>;
118 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
119 resets = <&rctl STM32_RESET(APB1L, 20U)>;
130 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
142 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
153 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
163 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
171 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
172 resets = <&rctl STM32_RESET(APB1L, 1U)>;
193 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
194 resets = <&rctl STM32_RESET(APB1L, 2U)>;
215 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
216 resets = <&rctl STM32_RESET(APB1L, 3U)>;
237 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
238 resets = <&rctl STM32_RESET(APB1L, 5U)>;
259 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
260 resets = <&rctl STM32_RESET(APB2, 13U)>;
276 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
277 resets = <&rctl STM32_RESET(APB2, 18U)>;
300 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
312 clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
331 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
341 clocks = <&rcc STM32_CLOCK(AHB2, 22U)>,
343 resets = <&rctl STM32_RESET(AHB2, 22U)>;
351 clocks = <&rcc STM32_CLOCK(AHB2, 23U)>,
353 resets = <&rctl STM32_RESET(AHB2, 23U)>;
361 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
371 clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
373 <&rcc STM32_CLOCK(AHB2, 20U)>;
385 clocks = <&rcc STM32_CLOCK(AHB3, 9U)>,
387 <&rcc STM32_CLOCK(AHB2, 20U)>;