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Searched refs:DT_REG_ADDR (Results 1 – 25 of 404) sorted by relevance

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/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c21 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
24 MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
28 MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
39 MMU_REGION_FLAT_ENTRY("MU2_A", DT_REG_ADDR(DT_NODELABEL(mu2_a)),
43 MMU_REGION_FLAT_ENTRY("OUTBOX", DT_REG_ADDR(DT_NODELABEL(outbox)),
46 MMU_REGION_FLAT_ENTRY("INBOX", DT_REG_ADDR(DT_NODELABEL(inbox)),
49 MMU_REGION_FLAT_ENTRY("STREAM", DT_REG_ADDR(DT_NODELABEL(stream)),
52 MMU_REGION_FLAT_ENTRY("HOST_RAM", DT_REG_ADDR(DT_NODELABEL(host_ram)),
/Zephyr-latest/soc/snps/emsk/
Dsoc_config.c21 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x4); in soc_early_init_hook()
22 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x10); in soc_early_init_hook()
25 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x4); in soc_early_init_hook()
26 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x10); in soc_early_init_hook()
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h15 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
18 #define L2_VIRTUAL_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0virtual)))
21 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1)))
80 #define ADSP_L1CC_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap)))
81 #define ADSP_CxL1CCAP_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap)))
82 #define ADSP_CxL1CCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccfg)))
83 #define ADSP_CxL1PCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1pcfg)))
102 #define DFL2MM_REG (DT_REG_ADDR(DT_NODELABEL(hsbcap)))
166 #define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm)))
[all …]
/Zephyr-latest/boards/snps/emsdp/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
38 DT_REG_ADDR(DT_INST(0, mmio_sram)),
/Zephyr-latest/boards/snps/em_starterkit/
Darc_mpu_regions.c19 DT_REG_ADDR(DT_INST(0, arc_iccm)),
26 DT_REG_ADDR(DT_INST(0, arc_dccm)),
34 DT_REG_ADDR(DT_INST(0, arc_xccm)),
41 DT_REG_ADDR(DT_INST(0, arc_yccm)),
49 DT_REG_ADDR(DT_INST(0, mmio_sram)),
/Zephyr-latest/boards/snps/nsim/arc_classic/
Darc_mpu_regions.c30 DT_REG_ADDR(DT_INST(0, arc_iccm)),
37 DT_REG_ADDR(DT_INST(0, arc_dccm)),
44 DT_REG_ADDR(DT_INST(0, arc_xccm)),
51 DT_REG_ADDR(DT_INST(0, arc_yccm)),
62 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
81 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
/Zephyr-latest/soc/nuvoton/numaker/m55m1x/
Dmpu_regions.c21 DT_REG_ADDR(DT_NODELABEL(itcm)),
22 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
28 DT_REG_ADDR(DT_NODELABEL(dtcm)),
29 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
/Zephyr-latest/boards/arm/mps2/
Dpinmux.c32 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
34 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
36 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2)))
38 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3)))
/Zephyr-latest/soc/espressif/esp32/
Dmemory.h8 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
14 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1))
22 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))
91 #define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
93 #define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
95 #define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
/Zephyr-latest/boards/snps/iotdk/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
Dsoc.c21 DT_REG_ADDR(id),\
36 DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
44 DT_REG_ADDR(DT_NODELABEL(gem0)),
50 DT_REG_ADDR(DT_NODELABEL(gem1)),
102 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in soc_reset_hook()
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
Dsoc.c21 DT_REG_ADDR(id),\
36 DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
44 DT_REG_ADDR(DT_NODELABEL(gem0)),
50 DT_REG_ADDR(DT_NODELABEL(gem1)),
102 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in soc_reset_hook()
/Zephyr-latest/soc/microchip/mec/mec172x/
Ddevice_power.c16 ((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
18 ((struct ecia_named_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
20 ((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
22 ((struct peci_regs *)(DT_REG_ADDR(DT_NODELABEL(peci0))))
24 ((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
26 ((struct tfdp_regs *)(DT_REG_ADDR(DT_NODELABEL(tfdp0))))
28 ((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
30 ((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart1))))
34 ((uintptr_t)(DT_REG_ADDR(DT_NODELABEL(bbram))))
36 #define BTMR16_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer0))
[all …]
/Zephyr-latest/soc/espressif/esp32s2/
Dmemory.h11 #define SRAM_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
57 #define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
59 #define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
61 #define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_rv32m1.c17 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
18 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
20 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
21 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
Dpinctrl_nxp_port.c19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
20 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
21 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
23 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
26 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
29 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portf)),
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c24 DT_REG_ADDR(DT_NODELABEL(ccm)),
29 DT_REG_ADDR(DT_NODELABEL(ana_pll)),
34 DT_REG_ADDR(DT_NODELABEL(iomuxc)),
39 DT_REG_ADDR(DT_NODELABEL(rdc)),
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h12 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
15 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1)))
91 #define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm)))
98 #define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm)))
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/src/
Dmain.c12 #define ADDR_MEM_CACHE DT_REG_ADDR(DT_NODELABEL(mem_cache))
13 #define ADDR_MEM_CACHE_SW DT_REG_ADDR(DT_NODELABEL(mem_cache_sw))
14 #define ADDR_MEM_NON_CACHE_SW DT_REG_ADDR(DT_NODELABEL(mem_noncache_sw))
15 #define ADDR_MEM_DMA_SW DT_REG_ADDR(DT_NODELABEL(mem_dma_sw))
16 #define ADDR_MEM_CACHE_BIG_SW DT_REG_ADDR(DT_NODELABEL(mem_cache_sw_big))
17 #define ADDR_MEM_CACHE_DMA_SW DT_REG_ADDR(DT_NODELABEL(mem_cache_cache_dma_multi))
/Zephyr-latest/soc/espressif/esp32s3/
Dmemory.h10 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
12 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1))
16 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))
102 #define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
104 #define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dasm_memory_management.h18 movi \az, DT_REG_ADDR(DT_NODELABEL(hsbcap))
26 movi \az, DT_REG_ADDR(DT_NODELABEL(lsbpm))
44 movi \au, DT_REG_ADDR(DT_NODELABEL(hsbcap))
51 movi \az, DT_REG_ADDR(DT_NODELABEL(hsbpm))
/Zephyr-latest/soc/st/stm32/stm32h7x/
Dsections.ld18 . = ABSOLUTE(DT_REG_ADDR(sram_eth_node));
20 . = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 256;
22 . = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 16K;
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
Dmmu_regions.c15 DT_REG_ADDR(DT_NODELABEL(sysmgr)),
20 DT_REG_ADDR(DT_NODELABEL(clock)),
25 DT_REG_ADDR(DT_NODELABEL(uart0)),
/Zephyr-latest/soc/infineon/cat1b/cyw20829/
Dapp_header.c41 .boot_strap_addr = DT_REG_ADDR(DT_NODELABEL(bootstrap_region)) -
42 DT_REG_ADDR(DT_NODELABEL(flash0)),
43 .boot_strap_dst_addr = DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)),
/Zephyr-latest/soc/nxp/imx/imx9/imx91/
Dmmu_regions.c20 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
23 MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
27 MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),

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