1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ 8 9 #include <zephyr/devicetree.h> 10 #include <adsp-vectors.h> 11 12 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) 13 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) 14 15 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) 16 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) 17 18 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10) 19 20 /* Linker-usable RAM region */ 21 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE) 22 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) 23 24 #define SRAM_BANK_SIZE (64 * 1024) 25 #define EBB_SEG_SIZE 32 26 #define HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE) 27 28 /* div_round_up, but zephyr version is not defined for assembler where this is also used */ 29 #define HPSRAM_SEGMENTS (HPSRAM_EBB_COUNT + EBB_SEG_SIZE - 1) / EBB_SEG_SIZE 30 #define HPSRAM_MEMMASK(idx) ((1ULL << (HPSRAM_EBB_COUNT - EBB_SEG_SIZE * idx)) - 1) 31 32 /* L3 region (IMR), located in host memory */ 33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1))) 34 35 /* The rimage tool produces two blob addresses we need to find: one is 36 * our bootloader code block which starts at its entry point, the 37 * other is the "manifest" containing the HP-SRAM data to unpack, 38 * which appears 24k earlier in the DMA'd file, and thus in IMR 39 * memory. There's no ability to change this offset, it's a magic 40 * number from rimage we simply need to honor. 41 */ 42 43 #define IMR_BOOT_LDR_DATA_BASE 0xB0039000 44 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 45 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000) 46 47 #define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038 48 49 /* L1 init */ 50 #define ADSP_L1CC_ADDR (0x9F080080) 51 #define ADSP_CxL1CCAP_ADDR (ADSP_L1CC_ADDR + 0x0000) 52 #define ADSP_CxL1CCFG_ADDR (ADSP_L1CC_ADDR + 0x0004) 53 #define ADSP_CxL1PCFG_ADDR (ADSP_L1CC_ADDR + 0x0008) 54 55 #if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)) 56 57 #define ADSP_CxL1CCAP_REG (*(volatile uint32_t *)(ADSP_CxL1CCAP_ADDR)) 58 #define ADSP_CxL1CCFG_REG (*(volatile uint32_t *)(ADSP_CxL1CCFG_ADDR)) 59 #define ADSP_CxL1PCFG_REG (*(volatile uint32_t *)(ADSP_CxL1PCFG_ADDR)) 60 61 #endif /* (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)) */ 62 63 /* The number of set associative cache way supported on L1 Data Cache */ 64 #define ADSP_CxL1CCAP_DCMWC ((ADSP_CxL1CCAP_REG >> 16) & 7) 65 /* The number of set associative cache way supported on L1 Instruction Cache */ 66 #define ADSP_CxL1CCAP_ICMWC ((ADSP_CxL1CCAP_REG >> 20) & 7) 67 68 #ifndef _ASMLANGUAGE 69 /* L2 Local Memory Management */ 70 71 struct cavs_hpsram_regs { 72 /** @brief power gating control */ 73 uint32_t HSxPGCTL; 74 /** @brief retention mode control */ 75 uint32_t HSxRMCTL; 76 /** @brief power gating status */ 77 uint32_t HSxPGISTS; 78 }; 79 80 struct cavs_lpsram_regs { 81 /** @brief power gating control */ 82 uint32_t USxPGCTL; 83 /** @brief retention mode control */ 84 uint32_t USxRMCTL; 85 /** @brief power gating status */ 86 uint32_t USxPGISTS; 87 }; 88 #endif /* _ASMLANGUAGE */ 89 90 /* These registers are for the L2 HP SRAM bank power management control and status.*/ 91 #define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm))) 92 #define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm))) 93 94 #define HPSRAM_REGS(block_idx) ((volatile struct cavs_hpsram_regs *const) \ 95 (L2_HSBPM_BASE + L2_HSBPM_SIZE * (block_idx))) 96 97 /* These registers are for the L2 LP SRAM bank power management control and status.*/ 98 #define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm))) 99 #define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm))) 100 101 #define LPSRAM_REGS(block_idx) ((volatile struct cavs_lpsram_regs *const) \ 102 (L2_LSBPM_BASE + L2_LSBPM_SIZE * (block_idx))) 103 104 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */ 105
