1 /*
2 * Copyright 2022-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #define DT_DRV_COMPAT nxp_port_pinmux
9
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/logging/log.h>
13 #include <fsl_clock.h>
14
15 LOG_MODULE_REGISTER(pinctrl_nxp_port, CONFIG_PINCTRL_LOG_LEVEL);
16
17 /* Port register addresses. */
18 static PORT_Type *ports[] = {
19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
20 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
21 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
22 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
23 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
24 #endif
25 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
26 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
27 #endif
28 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 5
29 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portf)),
30 #endif
31 };
32
33 #define PIN(mux) (((mux) & 0xFC00000) >> 22)
34 #define PORT(mux) (((mux) & 0xF0000000) >> 28)
35 #define PINCFG(mux) ((mux) & Z_PINCTRL_NXP_PORT_PCR_MASK)
36
37 struct pinctrl_mcux_config {
38 const struct device *clock_dev;
39 clock_control_subsys_t clock_subsys;
40 };
41
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)42 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
43 uintptr_t reg)
44 {
45 for (uint8_t i = 0; i < pin_cnt; i++) {
46 PORT_Type *base = ports[PORT(pins[i])];
47 uint8_t pin = PIN(pins[i]);
48 uint16_t mux = PINCFG(pins[i]);
49
50 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux;
51 }
52 return 0;
53 }
54
pinctrl_mcux_init(const struct device * dev)55 static int pinctrl_mcux_init(const struct device *dev)
56 {
57 const struct pinctrl_mcux_config *config = dev->config;
58 int err;
59
60 if (!device_is_ready(config->clock_dev)) {
61 LOG_ERR("clock control device not ready");
62 return -ENODEV;
63 }
64
65 err = clock_control_on(config->clock_dev, config->clock_subsys);
66 if (err) {
67 LOG_ERR("failed to enable clock (err %d)", err);
68 return -EINVAL;
69 }
70
71 return 0;
72 }
73
74 #if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, nxp_kinetis_sim))
75 #define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
76 CLK_GATE_DEFINE(DT_INST_CLOCKS_CELL(n, offset), DT_INST_CLOCKS_CELL(n, bits))
77 #elif DT_HAS_COMPAT_STATUS_OKAY(nxp_scg_k4)
78 #define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
79 (DT_INST_CLOCKS_CELL(n, mrcc_offset) == 0 \
80 ? 0 \
81 : MAKE_MRCC_REGADDR(MRCC_BASE, DT_INST_CLOCKS_CELL(n, mrcc_offset)))
82 #else
83 #define PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n) \
84 DT_INST_CLOCKS_CELL(n, name)
85 #endif
86
87 #define PINCTRL_MCUX_INIT(n) \
88 static const struct pinctrl_mcux_config pinctrl_mcux_##n##_config = {\
89 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
90 .clock_subsys = (clock_control_subsys_t) \
91 PINCTRL_MCUX_DT_INST_CLOCK_SUBSYS(n), \
92 }; \
93 \
94 DEVICE_DT_INST_DEFINE(n, \
95 &pinctrl_mcux_init, \
96 NULL, \
97 NULL, &pinctrl_mcux_##n##_config, \
98 PRE_KERNEL_1, \
99 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
100 NULL);
101
102 DT_INST_FOREACH_STATUS_OKAY(PINCTRL_MCUX_INIT)
103
