1 /*
2 * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
3 * Copyright (c) 2022 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT openisa_rv32m1_pinmux
9
10 #include <zephyr/drivers/pinctrl.h>
11
12 #include <fsl_clock.h>
13 #include <soc.h>
14
15 /* Port register addresses. */
16 static PORT_Type *ports[] = {
17 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
18 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
20 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
21 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
22 };
23
24 #define PIN(mux) (((mux) & 0xFC00000) >> 22)
25 #define PORT(mux) (((mux) & 0xF0000000) >> 28)
26 #define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK)
27
28 struct pinctrl_rv32m1_config {
29 clock_ip_name_t clock_ip_name;
30 };
31
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)32 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
33 uintptr_t reg)
34 {
35 for (uint8_t i = 0; i < pin_cnt; i++) {
36 PORT_Type *base = ports[PORT(pins[i])];
37 uint8_t pin = PIN(pins[i]);
38 uint16_t mux = PINCFG(pins[i]);
39
40 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux;
41 }
42 return 0;
43 }
44
pinctrl_rv32m1_init(const struct device * dev)45 static int pinctrl_rv32m1_init(const struct device *dev)
46 {
47 const struct pinctrl_rv32m1_config *config = dev->config;
48
49 CLOCK_EnableClock(config->clock_ip_name);
50
51 return 0;
52 }
53
54 #define PINCTRL_RV32M1_INIT(n) \
55 static const struct pinctrl_rv32m1_config pinctrl_rv32m1_##n##_config = {\
56 .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
57 }; \
58 \
59 DEVICE_DT_INST_DEFINE(n, \
60 &pinctrl_rv32m1_init, \
61 NULL, \
62 NULL, &pinctrl_rv32m1_##n##_config, \
63 PRE_KERNEL_1, \
64 CONFIG_PINCTRL_RV32M1_INIT_PRIORITY, \
65 NULL);
66
67 DT_INST_FOREACH_STATUS_OKAY(PINCTRL_RV32M1_INIT)
68
