1 /* 2 * Copyright 2020-2022,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/arch/arm64/arm_mmu.h> 8 #include <zephyr/devicetree.h> 9 #include <zephyr/sys/util.h> 10 11 static const struct arm_mmu_region mmu_regions[] = { 12 13 MMU_REGION_FLAT_ENTRY("GIC", 14 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0), 15 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0), 16 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 17 18 MMU_REGION_FLAT_ENTRY("GIC", 19 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1), 20 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), 21 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 22 23 MMU_REGION_FLAT_ENTRY("CCM", 24 DT_REG_ADDR(DT_NODELABEL(ccm)), 25 DT_REG_SIZE(DT_NODELABEL(ccm)), 26 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 27 28 MMU_REGION_FLAT_ENTRY("ANA_PLL", 29 DT_REG_ADDR(DT_NODELABEL(ana_pll)), 30 DT_REG_SIZE(DT_NODELABEL(ana_pll)), 31 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 32 33 MMU_REGION_FLAT_ENTRY("IOMUXC", 34 DT_REG_ADDR(DT_NODELABEL(iomuxc)), 35 DT_REG_SIZE(DT_NODELABEL(iomuxc)), 36 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 37 38 MMU_REGION_FLAT_ENTRY("RDC", 39 DT_REG_ADDR(DT_NODELABEL(rdc)), 40 DT_REG_SIZE(DT_NODELABEL(rdc)), 41 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), 42 43 MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_imx_iuart, 44 (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) 45 }; 46 47 const struct arm_mmu_config mmu_config = { 48 .num_regions = ARRAY_SIZE(mmu_regions), 49 .mmu_regions = mmu_regions, 50 }; 51
