1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ 8 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/toolchain.h> 12 #include <adsp-vectors.h> 13 #include <mem_window.h> 14 15 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) 16 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) 17 18 #define L2_VIRTUAL_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0virtual))) 19 #define L2_VIRTUAL_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0virtual))) 20 21 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) 22 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) 23 24 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10) 25 26 /* Linker-usable RAM region */ 27 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE) 28 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) 29 30 31 /* L3 region (IMR), located in host memory */ 32 33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1))) 34 #define L3_MEM_SIZE (DT_REG_SIZE(DT_NODELABEL(imr1))) 35 #define L3_MEM_PAGE_SIZE (DT_PROP(DT_NODELABEL(imr1), block_size)) 36 37 /* The rimage tool produces two blob addresses we need to find: one is 38 * our bootloader code block which starts at its entry point, the 39 * other is the "manifest" containing the HP-SRAM data to unpack, 40 * which appears 24k earlier in the DMA'd file, and thus in IMR 41 * memory. There's no ability to change this offset, it's a magic 42 * number from rimage we simply need to honor. 43 */ 44 /* FIXME: most of these macros aren't related to the bootloader */ 45 #define IMR_BOOT_LDR_MANIFEST_OFFSET 0x42000 46 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 47 #define IMR_BOOT_LDR_MANIFEST_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_MANIFEST_OFFSET) 48 49 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x180 50 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE) 51 52 #define IMR_BOOT_LDR_LIT_SIZE 0x40 53 #define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ 54 IMR_BOOT_LDR_TEXT_ENTRY_SIZE) 55 56 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 57 #define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE) 58 59 #define IMR_BOOT_LDR_DATA_OFFSET 0x49000 60 #define IMR_BOOT_LDR_DATA_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_DATA_OFFSET) 61 #define IMR_BOOT_LDR_DATA_SIZE 0xA8000 62 63 #define IMR_BOOT_LDR_BSS_OFFSET 0x110000 64 #define IMR_BOOT_LDR_BSS_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_BSS_OFFSET) 65 #define IMR_BOOT_LDR_BSS_SIZE 0x40000 66 67 /* stack to be used at boot, when RAM is not yet powered up */ 68 #define IMR_BOOT_LDR_STACK_BASE (IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE) 69 #define IMR_BOOT_LDR_STACK_SIZE 0x1000 70 71 /* position of L3 heap, size of L3 heap - till end of the L3 memory */ 72 /* !!! FIXME: L3 heap base MUST be automatically calculated. !!! */ 73 #define IMR_L3_HEAP_BASE (IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE) 74 #define IMR_L3_HEAP_SIZE (L3_MEM_SIZE - \ 75 (IMR_L3_HEAP_BASE - L3_MEM_BASE_ADDR)) 76 77 #define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038 78 79 /* L1 init */ 80 #define ADSP_L1CC_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap))) 81 #define ADSP_CxL1CCAP_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccap))) 82 #define ADSP_CxL1CCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1ccfg))) 83 #define ADSP_CxL1PCFG_ADDR (DT_REG_ADDR(DT_NODELABEL(l1pcfg))) 84 85 #if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)) 86 87 #define ADSP_CxL1CCAP_REG (*(volatile uint32_t *)(ADSP_CxL1CCAP_ADDR)) 88 #define ADSP_CxL1CCFG_REG (*(volatile uint32_t *)(ADSP_CxL1CCFG_ADDR)) 89 #define ADSP_CxL1PCFG_REG (*(volatile uint32_t *)(ADSP_CxL1PCFG_ADDR)) 90 91 #endif /* (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)) */ 92 93 /* The number of set associative cache way supported on L1 Data Cache */ 94 #define ADSP_CxL1CCAP_DCMWC ((ADSP_CxL1CCAP_REG >> 16) & 7) 95 /* The number of set associative cache way supported on L1 Instruction Cache */ 96 #define ADSP_CxL1CCAP_ICMWC ((ADSP_CxL1CCAP_REG >> 20) & 7) 97 98 #ifndef _LINKER 99 /* L2 Local Memory Management */ 100 101 /* These registers are for the L2 memory control and status. */ 102 #define DFL2MM_REG (DT_REG_ADDR(DT_NODELABEL(hsbcap))) 103 104 struct ace_l2mm { 105 uint32_t l2mcap; 106 uint32_t l2mpat; 107 uint32_t l2mecap; 108 uint32_t l2mecs; 109 uint32_t l2hsbpmptr; 110 uint32_t l2usbpmptr; 111 uint32_t l2usbmrpptr; 112 uint32_t l2ucmrpptr; 113 uint32_t l2ucmrpdptr; 114 }; 115 116 #define ACE_L2MM ((volatile struct ace_l2mm *)DFL2MM_REG) 117 118 /* DfL2MCAP */ 119 struct ace_l2mcap { 120 uint32_t l2hss : 8; 121 uint32_t l2uss : 4; 122 uint32_t l2hsbs : 4; 123 uint32_t l2hs2s : 8; 124 uint32_t l2usbs : 5; 125 uint32_t l2se : 1; 126 uint32_t el2se : 1; 127 uint32_t rsvd32 : 1; 128 }; 129 130 #define ACE_L2MCAP ((volatile struct ace_l2mcap *)DFL2MM_REG) 131 ace_hpsram_get_bank_count(void)132static ALWAYS_INLINE uint32_t ace_hpsram_get_bank_count(void) 133 { 134 return ACE_L2MCAP->l2hss; 135 } 136 ace_lpsram_get_bank_count(void)137static ALWAYS_INLINE uint32_t ace_lpsram_get_bank_count(void) 138 { 139 return ACE_L2MCAP->l2uss; 140 } 141 142 struct ace_hpsram_regs { 143 /** @brief power gating control */ 144 uint8_t HSxPGCTL; 145 /** @brief retention mode control */ 146 uint8_t HSxRMCTL; 147 uint8_t reserved[2]; 148 /** @brief power gating status */ 149 uint8_t HSxPGISTS; 150 uint8_t reserved1[3]; 151 }; 152 153 struct ace_lpsram_regs { 154 /** @brief power gating control */ 155 uint8_t USxPGCTL; 156 /** @brief retention mode control */ 157 uint8_t USxRMCTL; 158 uint8_t reserved[2]; 159 /** @brief power gating status */ 160 uint8_t USxPGISTS; 161 uint8_t reserved1[3]; 162 }; 163 #endif 164 165 /* These registers are for the L2 HP SRAM bank power management control and status.*/ 166 #define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm))) 167 #define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm))) 168 169 #define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \ 170 (L2_HSBPM_BASE + L2_HSBPM_SIZE * (block_idx))) 171 172 /* These registers are for the L2 LP SRAM bank power management control and status.*/ 173 #define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm))) 174 #define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm))) 175 176 #define LPSRAM_REGS(block_idx) ((volatile struct ace_lpsram_regs *const) \ 177 (L2_LSBPM_BASE + L2_LSBPM_SIZE * (block_idx))) 178 179 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */ 180
