1 /* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 #pragma once 6 7 /* SRAM0 (192kB) instruction cache+memory */ 8 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0)) 9 #define SRAM0_CACHE_SIZE 0x10000 10 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0)) 11 12 /* SRAM1 (128kB) instruction/data memory */ 13 #define SRAM1_IRAM_START (SRAM0_IRAM_START + SRAM0_SIZE) 14 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1)) 15 #define SRAM1_SIZE DT_REG_SIZE(DT_NODELABEL(sram1)) 16 #define SRAM1_DRAM_END (SRAM1_DRAM_START + SRAM1_SIZE) 17 #define SRAM1_RESERVED_SIZE 0x8000 18 #define SRAM1_DRAM_USER_START (SRAM1_DRAM_START + SRAM1_RESERVED_SIZE) 19 #define SRAM1_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START) 20 21 /* SRAM2 (200kB) data memory */ 22 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2)) 23 #define SRAM2_DRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram2)) 24 #define SRAM2_DRAM_SHM_SIZE 0x2000 25 #define SRAM2_DRAM_END (SRAM2_DRAM_START + SRAM2_DRAM_SIZE) 26 #define SRAM2_DRAM_USER_START (SRAM2_DRAM_START + SRAM2_DRAM_SHM_SIZE) 27 #define SRAM2_DRAM_USER_SIZE (SRAM2_DRAM_END - SRAM2_DRAM_USER_START) 28 29 /** Simplified memory map for the bootloader. 30 * Make sure the bootloader can load into main memory without overwriting itself. 31 * 32 * ESP32 ROM static data usage is as follows: 33 * - 0x3ffae000 - 0x3ffb0000 (Reserved: data memory for ROM functions) 34 * - 0x3ffb0000 - 0x3ffe0000 (RAM bank 1 for application usage) 35 * - 0x3ffe0000 - 0x3ffe0440 (Reserved: data memory for ROM PRO CPU) 36 * - 0x3ffe3f20 - 0x3ffe4350 (Reserved: data memory for ROM APP CPU) 37 * - 0x3ffe4350 - 0x3ffe5230 (BT shm buffers) 38 * - 0x3ffe8000 - 0x3fffffff (RAM bank 2 for application usage) 39 */ 40 41 #define DRAM1_PROCPU_RESERVED_START 0x3ffe0000 42 #define DRAM1_APPCPU_RESERVED_START 0x3ffe3f20 43 #define DRAM1_BT_SHM_BUFFERS_START 0x3ffe4350 44 #define DRAM1_BT_SHM_BUFFERS_END 0x3ffe5230 45 46 /* The address is a limit set manually for AMP build */ 47 #define DRAM1_AMP_SHM_BUFFERS_END 0x3ffe9800 48 49 /* Convert IRAM address to its DRAM counterpart in SRAM1 memory */ 50 #define SRAM1_IRAM_DRAM_CALC(addr_iram) (SRAM1_SIZE - (addr_iram - SRAM1_IRAM_START) + \ 51 SRAM1_DRAM_START) 52 /* Convert DRAM address to its IRAM counterpart in SRAM1 memory */ 53 #define SRAM1_DRAM_IRAM_CALC(addr_dram) (SRAM1_SIZE - (addr_dram - SRAM1_DRAM_START) + \ 54 SRAM1_IRAM_START) 55 56 /* Set bootloader segments size */ 57 #define BOOTLOADER_DRAM_SEG_LEN 0x7a00 58 #define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x4000 59 #define BOOTLOADER_IRAM_SEG_LEN 0xa000 60 61 /* Start of the lower region is determined by region size and the end of the higher region */ 62 #define BOOTLOADER_DRAM_SEG_START 0x3ffe8000 63 #define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_DRAM_SEG_START + BOOTLOADER_DRAM_SEG_LEN) 64 #define BOOTLOADER_IRAM_LOADER_SEG_START 0x40078000 65 #define BOOTLOADER_IRAM_SEG_START 0x400a0000 66 67 /* The `USER_IRAM_END` represents the end of staticaly allocated memory. 68 * This address is where 2nd stage bootloader starts allocating memory. 69 * The `iram_loader_seg` which is the last memory the bootloader runs from 70 * resides in the SRAM0 'cache' area, the `user_iram_end` applies for 71 * all build cases - Simple boot and the MCUboot application. 72 */ 73 #if defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32_APPCPU) 74 #define USER_IRAM_END SRAM1_DRAM_IRAM_CALC(DRAM1_AMP_SHM_BUFFERS_END) 75 #else 76 #define USER_IRAM_END SRAM1_DRAM_IRAM_CALC(SRAM1_DRAM_USER_START) 77 #endif 78 79 /* AMP memory */ 80 #if defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32_APPCPU) 81 #define APPCPU_IRAM_SIZE CONFIG_ESP_APPCPU_IRAM_SIZE 82 #define APPCPU_DRAM_SIZE CONFIG_ESP_APPCPU_DRAM_SIZE 83 #else 84 #define APPCPU_IRAM_SIZE 0 85 #define APPCPU_DRAM_SIZE 0 86 #endif 87 88 #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE) 89 90 /* Flash */ 91 #ifdef CONFIG_FLASH_SIZE 92 #define FLASH_SIZE CONFIG_FLASH_SIZE 93 #else 94 #define FLASH_SIZE 0x400000 95 #endif 96 97 /* Cached memories */ 98 #define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE 99 #define IROM_SEG_ORG 0x400d0000 100 #define IROM_SEG_LEN (FLASH_SIZE - 0x1000) 101 #define DROM_SEG_ORG 0x3f400000 102 #define DROM_SEG_LEN (FLASH_SIZE - 0x1000) 103
