1 /* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 #pragma once 6 7 /* SRAM0 (32k), SRAM1 (416k), SRAM2 (64k) memories 8 * Ibus and Dbus address space 9 */ 10 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0)) 11 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0)) 12 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1)) 13 #define SRAM1_IRAM_START (SRAM0_IRAM_START + SRAM0_SIZE) 14 #define SRAM_USER_IRAM_START (SRAM0_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) 15 16 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2)) 17 #define SRAM2_SIZE DT_REG_SIZE(DT_NODELABEL(sram2)) 18 #define SRAM2_USER_DRAM_START (SRAM2_DRAM_START + CONFIG_ESP32S3_DATA_CACHE_SIZE) 19 #define SRAM2_USER_DRAM_SIZE (SRAM2_SIZE - CONFIG_ESP32S3_DATA_CACHE_SIZE) 20 21 /** Simplified memory map for the bootloader. 22 * Make sure the bootloader can load into main memory without overwriting itself. 23 * 24 * ESP32-S3 ROM static data usage is as follows: 25 * - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only 26 * - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup 27 * - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup 28 * - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable) 29 * 30 * The 2nd stage bootloader can take space up to the end of ROM shared 31 * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). 32 */ 33 34 /* The offset between Dbus and Ibus. 35 * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. 36 */ 37 #define IRAM_DRAM_OFFSET 0x6f0000 38 #define DRAM_BUFFERS_START 0x3fcd7e00 39 #define DRAM_BUFFERS_END 0x3fce9704 40 #define DRAM_PROCPU_STACK_START 0x3fce9710 41 #define DRAM_STACK_START DRAM_PROCPU_STACK_START 42 #define DRAM_APPCPU_STACK_START 0x3fceb710 43 #define DRAM_ROM_BSS_DATA_START 0x3fcf0000 44 45 /* Set the limit for the application runtime dynamic allocations */ 46 #define DRAM_RESERVED_START DRAM_BUFFERS_END 47 48 /* For safety margin between bootloader data section and startup stacks */ 49 #define BOOTLOADER_STACK_OVERHEAD 0x0 50 #define BOOTLOADER_DRAM_SEG_LEN 0x15000 51 #define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1a00 52 #define BOOTLOADER_IRAM_SEG_LEN 0xc000 53 54 /* Base address used for calculating memory layout 55 * counted from Dbus backwards and back to the Ibus 56 */ 57 #define BOOTLOADER_USER_DRAM_END (DRAM_BUFFERS_START - BOOTLOADER_STACK_OVERHEAD) 58 59 /* Start of the lower region is determined by region size and the end of the higher region */ 60 #define BOOTLOADER_IRAM_LOADER_SEG_START \ 61 (BOOTLOADER_USER_DRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) 62 #define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) 63 #define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET) 64 #define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN) 65 66 /* The "USER_IRAM_END" represents the end of staticaly allocated memory. 67 * This address is where 2nd stage bootloader starts allocating memory, 68 * and it should not be overlapped by the user image. 69 * When there is no 2nd stage bootloader the bootstrapping is done 70 * by the so-called SIMPLE_BOOT. 71 * NOTE: AMP is supported only if MCUboot is enabled. 72 */ 73 #ifdef CONFIG_ESP_SIMPLE_BOOT 74 #define USER_DRAM_END BOOTLOADER_USER_DRAM_END 75 #else 76 #define USER_DRAM_END (BOOTLOADER_IRAM_LOADER_SEG_START - IRAM_DRAM_OFFSET) 77 #endif 78 #define USER_IRAM_END (USER_DRAM_END + IRAM_DRAM_OFFSET) 79 80 /* AMP */ 81 #if defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32S3_APPCPU) 82 #define APPCPU_IRAM_SIZE CONFIG_ESP_APPCPU_IRAM_SIZE 83 #define APPCPU_DRAM_SIZE CONFIG_ESP_APPCPU_DRAM_SIZE 84 #define AMP_COMM_SIZE DT_REG_SIZE(DT_NODELABEL(ipmmem0)) + DT_REG_SIZE(DT_NODELABEL(shm0)) + \ 85 DT_REG_SIZE(DT_NODELABEL(ipm0)) + DT_REG_SIZE(DT_NODELABEL(mbox0)) 86 #undef DRAM_RESERVED_START 87 #define DRAM_RESERVED_START 0x3fce5000 88 #else 89 #define APPCPU_IRAM_SIZE 0 90 #define APPCPU_DRAM_SIZE 0 91 #define AMP_COMM_SIZE 0 92 #endif 93 94 #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE) 95 96 /* Flash */ 97 #ifdef CONFIG_FLASH_SIZE 98 #define FLASH_SIZE CONFIG_FLASH_SIZE 99 #else 100 #define FLASH_SIZE 0x800000 101 #endif 102 103 /* Cached memory */ 104 #define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE 105 #define IROM_SEG_ORG 0x42000000 106 #define IROM_SEG_LEN FLASH_SIZE 107 #define DROM_SEG_ORG 0x3c000000 108 #define DROM_SEG_LEN FLASH_SIZE 109
