1 /* 2 * Copyright (c) 2021, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/arch/arm64/arm_mmu.h> 8 #include <zephyr/devicetree.h> 9 #include <zephyr/sys/util.h> 10 11 static const struct arm_mmu_region mmu_regions[] = { 12 13 /* System manager register that required by clock driver */ 14 MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER", 15 DT_REG_ADDR(DT_NODELABEL(sysmgr)), 16 DT_REG_SIZE(DT_NODELABEL(sysmgr)), 17 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), 18 19 MMU_REGION_FLAT_ENTRY("CLOCK", 20 DT_REG_ADDR(DT_NODELABEL(clock)), 21 DT_REG_SIZE(DT_NODELABEL(clock)), 22 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), 23 24 MMU_REGION_FLAT_ENTRY("UART0", 25 DT_REG_ADDR(DT_NODELABEL(uart0)), 26 DT_REG_SIZE(DT_NODELABEL(uart0)), 27 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), 28 29 MMU_REGION_FLAT_ENTRY("GIC", 30 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0), 31 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0), 32 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), 33 34 MMU_REGION_FLAT_ENTRY("GIC", 35 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1), 36 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), 37 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), 38 }; 39 40 const struct arm_mmu_config mmu_config = { 41 .num_regions = ARRAY_SIZE(mmu_regions), 42 .mmu_regions = mmu_regions, 43 }; 44
