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Searched +full:stm32 +full:- +full:dmamux (Results 1 – 25 of 39) sorted by relevance

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/Zephyr-latest/dts/bindings/dma/
Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMAMUX controller
7 The STM32 DMAMUX is a direct memory access multiplexer
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
[all …]
Dst,stm32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
9 Each stm32 soc with a DMA is of a special version type, which could be
11 or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
29 dma-offset:
32 offset in the table of channels when mapping to a DMAMUX
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 BDMA controller
7 The STM32 BDMA is a general-purpose direct memory access controller
10 BDMA clients connected to the STM32 BDMA controller must use the format
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
[all …]
/Zephyr-latest/drivers/dma/
DKconfig.stm326 # SPDX-License-Identifier: Apache-2.0
9 bool "STM32 DMA driver"
17 Driver for STM32 DMA V1, V2, V2bis and BDMA types.
45 a parameter of the dma-cell.
52 Enable DMAMUX support.
64 bool "STM32 BDMA driver"
72 int "STM32 DMAMUX init priority"
76 DMAMUX driver device must be init'd after the DMA (CONFIG_DMA_INIT_PRIORITY)
77 DMAMUX driver device initialization priority is greater than DMA one's
Ddmamux_stm32.c5 * SPDX-License-Identifier: Apache-2.0
9 * @brief Common part of DMAMUX drivers for stm32.
32 /* this is the configuration of one dmamux channel */
40 /* the table of all the dmamux channel */
47 /* this is the configuration of the dmamux IP */
99 if (dev_config->base == DT_REG_ADDR(DT_NODELABEL(dmamux1))) { in get_dma_fops()
105 if (dev_config->base == DT_REG_ADDR(DT_NODELABEL(dmamux2))) { in get_dma_fops()
110 __ASSERT(false, "Unknown dma base address %x", dev_config->base); in get_dma_fops()
117 /* device is the dmamux, id is the dmamux channel from 0 */ in dmamux_stm32_configure()
118 const struct dmamux_stm32_config *dev_config = dev->config; in dmamux_stm32_configure()
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dst,stm32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 QSPI device representation. A stm32 quadspi node would typically
9 pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
14 dma-names = "tx_rx";
19 compatible: "st,stm32-qspi"
21 include: [base.yaml, pinctrl-device.yaml]
32 pinctrl-0:
35 pinctrl-names:
41 hold a phandle reference to the dma controller (not the DMAMUX even if present),
45 When a DMAMUX is present and enabled, the channel is the dma one
[all …]
/Zephyr-latest/dts/arm/st/g0/
Dstm32g070.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 compatible = "st,stm32g070", "st,stm32g0", "simple-bus";
15 compatible = "st,stm32-usart", "st,stm32-uart";
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-timers";
38 interrupt-names = "global";
43 compatible = "st,stm32-pwm";
45 #pwm-cells = <3>;
49 dmamux1: dmamux@40020800 {
50 dma-requests= <53>;
Dstm32g071.dtsi6 * SPDX-License-Identifier: Apache-2.0
13 compatible = "st,stm32g071", "st,stm32g0", "simple-bus";
16 compatible = "st,stm32-usart", "st,stm32-uart";
25 compatible = "st,stm32-usart", "st,stm32-uart";
33 dmamux1: dmamux@40020800 {
34 dma-requests= <57>;
38 compatible = "st,stm32-ucpd";
46 compatible = "st,stm32-ucpd";
Dstm32g051.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g051", "st,stm32g0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
23 compatible = "st,stm32-counter";
29 compatible = "st,stm32-timers";
34 interrupt-names = "global";
39 compatible = "st,stm32-counter";
45 compatible = "st,stm32-timers";
50 interrupt-names = "global";
[all …]
Dstm32g050.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g050", "st,stm32g0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
25 compatible = "st,stm32-timers";
30 interrupt-names = "global";
37 dma-requests = <7>;
40 dmamux1: dmamux@40020800 {
41 dma-channels = <7>;
Dstm32g0b0.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g0b0", "st,stm32g0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-usart", "st,stm32-uart";
42 compatible = "st,stm32-timers";
47 interrupt-names = "global";
[all …]
Dstm32g0.dtsi3 * Copyright (c) 2019-2024 STMicroelectronics
6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
8 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv6-m.dtsi>
12 #include <zephyr/dt-bindings/clock/stm32g0_clock.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/adc.h>
[all …]
Dstm32g0b1.dtsi3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
5 * SPDX-License-Identifier: Apache-2.0
13 clk_hsi48: clk-hsi48 {
14 #clock-cells = <0>;
15 compatible = "st,stm32-hsi48-clock";
16 clock-frequency = <DT_FREQ_M(48)>;
22 compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
25 pinctrl: pin-controller@50000000 {
27 compatible = "st,stm32-gpio";
28 gpio-controller;
[all …]
/Zephyr-latest/dts/bindings/ospi/
Dst,stm32-ospi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 OSPI device representation. Enabling a stm32 octospi node in a board
9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
16 dma-names = "tx_rx";
21 compatible: "st,stm32-ospi"
23 include: [base.yaml, pinctrl-device.yaml]
34 pinctrl-0:
37 pinctrl-names:
40 clock-names:
50 - &dma1: dma controller phandle
[all …]
/Zephyr-latest/dts/arm/st/c0/
Dstm32c071.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32c071", "st,stm32c0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
24 compatible = "st,stm32-pwm";
26 #pwm-cells = <3>;
30 compatible = "st,stm32-counter";
36 compatible = "st,stm32-i2c-v2";
37 clock-frequency = <I2C_BITRATE_STANDARD>;
38 #address-cells = <1>;
[all …]
Dstm32c0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/dma/stm32_dma.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h745.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
[all …]
Dstm32h743.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
24 dmamux1: dmamux@40020800 {
25 dma-requests= <107>;
[all …]
Dstm32h723.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/display/panel.h>
11 #include <zephyr/dt-bindings/flash_controller/ospi.h>
15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <32>;
21 erase-block-size = <DT_SIZE_K(128)>;
23 max-erase-time = <4000>;
28 compatible = "st,stm32-uart";
[all …]
Dstm32h7a3.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &adc3;
15 compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <16>;
21 erase-block-size = <DT_SIZE_K(8)>;
23 max-erase-time = <3>;
[all …]
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/dts/arm/st/u0/
Dstm32u073.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32u073", "st,stm32u0", "simple-bus";
14 compatible = "st,stm32-i2c-v2";
15 clock-frequency = <I2C_BITRATE_STANDARD>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 interrupt-names = "combined";
26 compatible = "st,stm32-lptim";
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/st/g4/
Dstm32g491.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-fdcan";
16 reg-names = "m_can", "message_ram";
18 interrupt-names = "int0", "int1";
20 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
25 compatible = "st,stm32-timers";
30 interrupt-names = "brk", "up", "trgcom", "cc";
35 compatible = "st,stm32-pwm";
37 #pwm-cells = <3>;
[all …]
/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13 #include <zephyr/dt-bindings/clock/stm32_clock.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &quadspi;
26 clk_hsi48: clk-hsi48 {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <DT_FREQ_M(48)>;
35 compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
38 flash-controller@40022000 {
40 erase-block-size = <4096>;
[all …]

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