1/*
2 * Copyright (c) 2020 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7.dtsi>
8#include <zephyr/dt-bindings/display/panel.h>
9
10/ {
11	soc {
12		compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
13
14		flash-controller@52002000 {
15			flash0: flash@8000000 {
16				compatible = "st,stm32-nv-flash", "soc-nv-flash";
17				write-block-size = <32>;
18				erase-block-size = <DT_SIZE_K(128)>;
19				/* maximum erase time for a 128K sector */
20				max-erase-time = <4000>;
21			};
22		};
23
24		dmamux1: dmamux@40020800 {
25			dma-requests= <107>;
26		};
27
28		dmamux2: dmamux@58025800 {
29			dma-requests= <107>;
30		};
31
32		usbotg_fs: usb@40080000 {
33			compatible = "st,stm32-otgfs";
34			reg = <0x40080000 0x40000>;
35			interrupts = <98 0>, <99 0>, <100 0>, <101 0>;
36			interrupt-names = "ep1_out", "ep1_in", "wkup", "otgfs";
37			num-bidir-endpoints = <9>;
38			ram-size = <4096>;
39			maximum-speed = "full-speed";
40			clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
41				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
42			phys = <&otghs_fs_phy>;
43			status = "disabled";
44		};
45
46		ltdc: display-controller@50001000 {
47			compatible = "st,stm32-ltdc";
48			reg = <0x50001000 0x200>;
49			interrupts = <88 0>, <89 0>;
50			interrupt-names = "ltdc", "ltdc_er";
51			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
52			resets = <&rctl STM32_RESET(APB3, 4U)>;
53			status = "disabled";
54		};
55
56		rtc@58004000 {
57			bbram: backup_regs {
58				compatible = "st,stm32-bbram";
59				st,backup-regs = <32>;
60				status = "disabled";
61			};
62		};
63	};
64
65	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
66	sram0: memory@24000000 {
67		reg = <0x24000000 DT_SIZE_K(512)>;
68		compatible = "mmio-sram";
69	};
70
71	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
72	sram1: memory@30000000 {
73		reg = <0x30000000 DT_SIZE_K(128)>;
74		compatible = "zephyr,memory-region", "mmio-sram";
75		zephyr,memory-region = "SRAM1";
76	};
77
78	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
79	sram2: memory@30020000 {
80		compatible = "zephyr,memory-region", "mmio-sram";
81		reg = <0x30020000 DT_SIZE_K(128)>;
82		zephyr,memory-region = "SRAM2";
83	};
84
85	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
86	sram3: memory@30040000 {
87		compatible = "zephyr,memory-region", "mmio-sram";
88		reg = <0x30040000 DT_SIZE_K(32)>;
89		zephyr,memory-region = "SRAM3";
90	};
91
92	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
93	sram4: memory@38000000 {
94		reg = <0x38000000 DT_SIZE_K(64)>;
95		compatible = "zephyr,memory-region", "mmio-sram";
96		zephyr,memory-region = "SRAM4";
97	};
98
99	dtcm: memory@20000000 {
100		compatible = "zephyr,memory-region", "arm,dtcm";
101		reg = <0x20000000 DT_SIZE_K(128)>;
102		zephyr,memory-region = "DTCM";
103	};
104
105	itcm: memory@0 {
106		compatible = "zephyr,memory-region", "arm,itcm";
107		reg = <0x00000000 DT_SIZE_K(64)>;
108		zephyr,memory-region = "ITCM";
109	};
110
111	otghs_fs_phy: otghs_fs_phy {
112		compatible = "usb-nop-xceiv";
113		#phy-cells = <0>;
114	};
115
116	vref: vref {
117		io-channels = <&adc3 19>;
118	};
119
120	vbat: vbat {
121		io-channels = <&adc3 17>;
122	};
123};
124