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/Zephyr-latest/drivers/clock_control/
Dclock_control_wch_rcc.c32 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
96 RCC->CTLR &= ~RCC_PLLON; in clock_control_wch_rcc_init()
100 RCC->RSTSCKR |= RCC_LSION; in clock_control_wch_rcc_init()
101 while ((RCC->RSTSCKR & RCC_LSIRDY) == 0) { in clock_control_wch_rcc_init()
105 RCC->CTLR |= RCC_HSION; in clock_control_wch_rcc_init()
106 while ((RCC->CTLR & RCC_HSIRDY) == 0) { in clock_control_wch_rcc_init()
111 RCC->CTLR |= RCC_HSEON; in clock_control_wch_rcc_init()
112 while ((RCC->CTLR & RCC_HSERDY) == 0) { in clock_control_wch_rcc_init()
118 RCC->CFGR0 |= RCC_PLLSRC; in clock_control_wch_rcc_init()
120 RCC->CFGR0 &= ~RCC_PLLSRC; in clock_control_wch_rcc_init()
[all …]
/Zephyr-latest/dts/bindings/phy/
Dst,stm32u5-otghs-phy.yaml23 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
24 <&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
27 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
28 <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) OTGHS_SEL(2)>;
31 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
32 <&rcc STM32_SRC_PLL1_P OTGHS_SEL(1)>;
35 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
36 <&rcc (STM32_SRC_PLL1_P | STM32_CLOCK_DIV(2)) OTGHS_SEL(3)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi44 rcc: rcc@40021000 { label
49 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
50 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
61 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
69 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
77 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
85 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
93 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
100 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
109 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
[all …]
Dstm32l496.dtsi24 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
34 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
49 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN
64 clocks = <&rcc STM32_CLOCK(AHB2, 12U)>,
65 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
69 clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
70 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l431.dtsi28 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
45 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
53 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
83 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
[all …]
Dstm32l451.dtsi29 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
37 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
42 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
43 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
52 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
64 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
85 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
93 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
[all …]
Dstm32l471.dtsi20 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
28 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
81 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
102 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay31 &rcc {
59 &rcc {
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
69 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
75 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
81 <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay39 &rcc {
73 &rcc {
85 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
86 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
93 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
94 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
99 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
100 <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;
Dl4_i2c1_hsi_lptim1_lse.overlay36 &rcc {
64 &rcc {
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
76 <&rcc STM32_SRC_HSI I2C1_SEL(2)>,
77 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
83 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
Dl4_i2c1_sysclk_lptim1_lsi.overlay36 &rcc {
64 &rcc {
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
76 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>,
77 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
83 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
Df4_sdmmc48_pll.overlay10 /* clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;*/
11 clocks = <&rcc STM32_SRC_PLLI2S_Q CK48M_SEL(1)>;
25 clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
27 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
28 /* <&rcc STM32_SRC_CK48 SDIO_SEL(0)>; */
/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi45 rcc: rcc@50000000 { label
46 compatible = "st,stm32mp1-rcc";
51 compatible = "st,stm32-rcc-rctl";
89 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
97 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
105 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
113 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
121 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
129 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
137 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
138 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
[all …]
Dstm32h5.dtsi135 clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
149 rcc: rcc@44020c00 { label
150 compatible = "st,stm32u5-rcc";
156 compatible = "st,stm32-rcc-rctl";
193 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
201 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
209 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
217 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
225 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
231 clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi14 rcc: rcc@40021000 { label
17 * prescaler in the RCC register
19 compatible = "st,stm32f1-rcc";
28 clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
38 clocks = <&rcc STM32_CLOCK(APB1, 22U)>,
42 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
53 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
63 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
71 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
88 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f1-rcc.yaml6 Adds the ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f1-rcc"
11 include: st,stm32-rcc.yaml
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi107 clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
135 rcc: rcc@40023800 { label
136 compatible = "st,stm32-rcc";
141 compatible = "st,stm32-rcc-rctl";
172 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
180 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
188 clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
196 clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
204 clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
212 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
[all …]
Dstm32f765.dtsi37 clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
45 clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
66 clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
77 clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
78 <&rcc STM32_CLOCK(AHB1, 26U)>,
79 <&rcc STM32_CLOCK(AHB1, 27U)>,
80 <&rcc STM32_CLOCK(AHB1, 28U)>;
87 clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
88 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
/Zephyr-latest/dts/arm/st/f4/
Dstm32f412.dtsi23 clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
39 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
47 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
54 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
75 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
85 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
96 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
112 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
135 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
[all …]
Dstm32f446.dtsi26 clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
37 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
46 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
55 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
66 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
83 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
84 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
96 clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
97 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
[all …]
Dstm32f405.dtsi26 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
34 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
42 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
49 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
58 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
67 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
76 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
131 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi153 rcc: rcc@58024400 { label
154 compatible = "st,stm32h7-rcc";
159 compatible = "st,stm32-rcc-rctl";
190 clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
198 clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
206 clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
214 clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
222 clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
230 clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
238 clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
[all …]
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
Dnucleo_f411re.overlay14 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;

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