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/Zephyr-latest/dts/bindings/pinctrl/
Dwch,afio.yaml2 # SPDX-License-Identifier: Apache-2.0
13 "#address-cells":
16 "#size-cells":
20 child-binding:
23 child-binding:
25 The grandchild nodes group pins that share the same pin configuration.
28 - name: pincfg-node.yaml
29 property-allowlist:
30 - bias-high-impedance
31 - bias-pull-up
[all …]
Dgd,gd32-pinctrl-afio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required). Only
[all …]
Dnxp,imx8m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 fields in a group select the pins to be configured, and the remaining
9 devicetree properties set configuration values for those pins
10 for example, here is an group configuring UART2 pins:
15 drive-strength = "40-ohm";
16 slew-rate = "slow";
20 Both pins will be configured with a slow slew rate, and maximum drive
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1
28 drive-open-drain: ODE=1
[all …]
Dgd,gd32-pinctrl-af.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required).
[all …]
Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
27 - "disable"
[all …]
Drenesas,rzg-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
10 device-pinmux {
15 drive-strength = <1>;
18 device-spins {
19 pins = <BSP_IO_XSPI_IO0>, <BSP_IO_XSPI_IO4>;
20 input-enable;
22 drive-strength = <2>;
27 compatible: renesas,rzg-pinctrl
34 reg-names:
[all …]
Dnxp,imx8mp-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 fields in a group select the pins to be configured, and the remaining
9 devicetree properties set configuration values for those pins
10 for example, here is an group configuring LPUART1 pins:
15 bias-pull-up;
16 slew-rate = "slow";
17 drive-strength = "x1";
21 Both pins will be configured with a slow slew rate, and minimum drive
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1, PE=1
[all …]
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 fields in a group select the pins to be configured, and the remaining
9 devicetree properties set configuration values for those pins
10 for example, here is an group configuring LPUART1 pins:
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
[all …]
/Zephyr-latest/dts/bindings/misc/
Dintel,timeaware-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "intel,timeaware-gpio"
14 timer-clock:
19 max-pins:
22 description: Total number of available pins
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Drd_rw612_bga.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Connect JP19 and J5 pins 4-5 */
10 compatible = "test-spi-loopback-slow";
12 spi-max-frequency = <500000>;
15 compatible = "test-spi-loopback-fast";
17 spi-max-frequency = <16000000>;
Dnucleo_f746zg.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Arduino Header pins: MOSI:D11, MISO:D12 */
11 dma-names = "tx", "rx";
13 compatible = "test-spi-loopback-slow";
15 spi-max-frequency = <500000>;
18 compatible = "test-spi-loopback-fast";
20 spi-max-frequency = <16000000>;
Dnucleo_f767zi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Arduino Header pins: MOSI:D11, MISO:D12 */
11 dma-names = "tx", "rx";
13 compatible = "test-spi-loopback-slow";
15 spi-max-frequency = <500000>;
18 compatible = "test-spi-loopback-fast";
20 spi-max-frequency = <16000000>;
Dcy8cproto_062_4343w.overlay2 compatible = "infineon,cat1-spi";
5 pinctrl-0 = <&p6_0_scb3_spi_m_mosi &p6_1_scb3_spi_m_miso &p6_2_scb3_spi_m_clk>;
6 pinctrl-names = "default";
7 cs-gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
10 compatible = "test-spi-loopback-slow";
12 spi-max-frequency = <2000000>;
15 compatible = "test-spi-loopback-fast";
17 spi-max-frequency = <3000000>;
26 /* Configure pin control bias mode for SPI pins */
29 drive-push-pull;
[all …]
Dcy8cproto_063_ble.overlay2 /* Configure pin control bias mode for SPI pins (MASTER) */
5 drive-push-pull;
10 input-enable;
15 drive-push-pull;
20 compatible = "infineon,cat1-spi";
23 pinctrl-0 = <&p10_0_scb1_spi_m_mosi &p10_1_scb1_spi_m_miso &p10_2_scb1_spi_m_clk>;
24 pinctrl-names = "default";
25 cs-gpios = <&gpio_prt10 3 GPIO_ACTIVE_LOW>;
28 compatible = "test-spi-loopback-slow";
30 spi-max-frequency = <200000>;
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dintel,blinky-pwm.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,blinky-pwm"
9 include: [pwm-controller.yaml, base.yaml]
15 reg-offset:
20 clock-frequency:
25 max-pins:
28 description: Maximum number of pins supported by platform
30 "#pwm-cells":
33 pwm-cells:
34 - channel
[all …]
/Zephyr-latest/dts/bindings/power/
Dst,stm32-pwr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-pwr"
14 wkup-pins-nb:
17 Max nbr of system wake-up pins.
18 For example wkup-pins-nb = <8>; on the stm32u5
20 wkup-pin-srcs:
23 Number of wake-up GPIO sources to select from for each wake-up pin.
25 wake-up pin.
27 For example, each wake-up pin on STM32U5 is associated with
28 4 wake-up sources, 3 of them correspond to GPIOs.
[all …]
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
40 address-width = <16>;
[all …]
/Zephyr-latest/boards/shields/adafruit_data_logger/
Dadafruit_data_logger.overlay2 * Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gpio-leds";
16 * pins "L1" and "Digital I/O 3".
24 * pins "L2" and "Digital I/O 4".
36 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
39 compatible = "zephyr,sdhc-spi-slot";
41 spi-max-frequency = <24000000>;
45 compatible = "zephyr,sdmmc-disk";
46 disk-name = "SD";
[all …]
/Zephyr-latest/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "vnd,pinctrl-device";
9 pinctrl-0 = <&test_device_default>;
10 pinctrl-names = "default";
17 pins are parsed correctly, but do not necessarily represent a
25 drive-push-pull;
29 drive-open-drain;
33 bias-disable;
37 bias-pull-up;
41 bias-pull-down;
[all …]
Dgd32f403z_eval.overlay3 * SPDX-License-Identifier: Apache-2.0
10 compatible = "vnd,pinctrl-device";
11 pinctrl-0 = <&test_device_default>;
12 pinctrl-names = "default";
19 pins are parsed correctly, but do not necessarily represent a
32 drive-push-pull;
36 drive-open-drain;
40 bias-disable;
44 bias-pull-up;
48 bias-pull-down;
[all …]
/Zephyr-latest/dts/bindings/regulator/
Dnordic,npm1300-regulator.yaml2 # SPDX-License-Identifier: Apache-2.0
16 compatible = "nordic,npm1300-regulator";
33 compatible: "nordic,npm1300-regulator"
38 dvs-gpios:
39 type: phandle-array
42 Set_dvs_mode will drive these pins as follows:
45 DVS mode 3 will drive the first and second pins
47 The effect of the mode change is defined by the enable-gpios
50 child-binding:
52 - name: regulator.yaml
[all …]
Dnordic,npm2100-regulator.yaml2 # SPDX-License-Identifier: Apache-2.0
16 compatible = "nordic,npm2100-regulator";
27 compatible: "nordic,npm2100-regulator"
32 dvs-gpios:
33 type: phandle-array
36 Set_dvs_mode will drive these pins as follows:
39 The effect of the mode change is defined by the mode-gpios
42 child-binding:
44 - name: regulator.yaml
45 property-allowlist:
[all …]
Dregulator-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO-controlled voltage of regulators
8 vccq_sd0: regulator-vccq-sd0 {
9 compatible = "regulator-gpio";
11 regulator-name = "SD0 VccQ";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <3300000>;
15 enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
20 regulator-boot-on;
23 In the above example, three GPIO pins are used for controlling the regulator:
[all …]
/Zephyr-latest/samples/drivers/jesd216/boards/
Dnrf52840dk_nrf52840_spi.overlay2 * Copyright (c) 2022-2023 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &mx25r64;
13 /* The mx25, on nrf52840dk/nrf52840, uses pins for spi0, spi1, spi2 and spi3
14 * to provide quad-spi feature. In individual specifications each of the spi
21 compatible = "nordic,nrf-spi";
23 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
24 pinctrl-0 = <&spi2_default>;
25 pinctrl-1 = <&spi2_sleep>;
26 pinctrl-names = "default", "sleep";
[all …]
/Zephyr-latest/boards/shields/seeed_xiao_round_display/
Dseeed_xiao_round_display.overlay4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
17 compatible = "voltage-divider";
18 io-channels = <&xiao_adc 0>;
19 output-ohms = <470000>;
20 full-ohms = <940000>;
24 compatible = "zephyr,lvgl-pointer-input";
33 compatible = "zephyr,mipi-dbi-spi";
34 spi-dev = <&xiao_spi>;
35 dc-gpios = <&xiao_d 3 GPIO_ACTIVE_HIGH>;
[all …]

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