1# Copyright (c) 2024 Epam Systems
2# Copyright (c) 2024 Renesas Electronics Corporation
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6  Below generic example shows of supported pinctrl definitions:
7
8    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
9    example_pins: device_pin {
10        device-pinmux {
11          pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
12                   <RZG_PINMUX(PORT_08, 2, 5)>;
13          bias_pull_up;
14          renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
15          drive-strength = <1>;
16        };
17
18        device-spins {
19          pins = <BSP_IO_XSPI_IO0>, <BSP_IO_XSPI_IO4>;
20          input-enable;
21          renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000);
22          drive-strength = <2>;
23        };
24      };
25
26
27compatible: renesas,rzg-pinctrl
28
29include: base.yaml
30properties:
31  reg:
32    required: true
33
34  reg-names:
35    required: true
36
37child-binding:
38  description: |
39    This RZG pins mux/cfg nodes description.
40
41  child-binding:
42    description: |
43      The RZG pinmux/pincfg configuration nodes description.
44
45    include:
46    - name: pincfg-node.yaml
47      property-allowlist:
48      - bias-disable
49      - bias-high-impedance
50      - bias-pull-down
51      - bias-pull-up
52      - bias-pull-pin-default
53      - drive-strength
54      - input-enable
55      - input-disable
56      - output-enable
57      - power-source
58      - low-power-enable
59      - low-power-disable
60
61    properties:
62      pinmux:
63        type: array
64        description: |
65          Pinmux configuration node.
66          Values are constructed from GPIO port number, pin number, and
67          alternate function configuration number using the RZG_PINMUX()
68          helper macro in pinctrl_rzg.h
69
70      pins:
71        type: array
72        description: |
73          Special Purpose pins configuration node.
74          Values are define in pinctrl_rzg.h.
75          Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
76
77      drive-strength:
78        type: int
79        default: 0
80        description: |
81          Maximum sink or source current in mA for pin which shell be selected
82          depending on device and pin group.
83
84      renesas,filter:
85        type: int
86        default: 0
87        description: |
88          Digital Noise Filter configuration for a pin which shell be defined
89          using RZG_FILTER_SET() helper macro in pinctrl_rzg.h to specify
90          FILNUM_m and FILCLKSEL_m. With 24Mhz external clock:
91          - min debounce time will be 166.666ns for FILNUM_m=0 and FILCLKSEL_m=0
92          - max debounce time will be 24ms for FILNUM_m=3 and FILCLKSEL_m=3.
93          This property intentionally redefined to avoid unnecessary conversation from usec to
94          FILNUM_m and FILCLKSEL_m values depending on external clock value as this configuration
95          is static.
96