1# Copyright (c), 2024 Nordic Semiconductor ASA
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Nordic nPM2100 PMIC
6
7  The PMIC has one boost converter and one LDO/LDSW.
8  The regulators need to be defined as child nodes,
9  strictly following the BOOST, LDOSW node names.
10  For example:
11
12  pmic@74 {
13    reg = <0x74>;
14    ...
15    regulators {
16      compatible = "nordic,npm2100-regulator";
17
18      BOOST {
19        /* all properties for BOOST */
20      };
21      LDOSW {
22        /* all properties for LDOSW */
23      };
24    };
25  };
26
27compatible: "nordic,npm2100-regulator"
28
29include: base.yaml
30
31properties:
32  dvs-gpios:
33    type: phandle-array
34    description: |
35      List of SOC GPIOs connected to PMIC GPIOs.
36      Set_dvs_mode will drive these pins as follows:
37        DVS mode 1 will enable the first pin
38        DVS mode 2 will enable the second pin
39      The effect of the mode change is defined by the mode-gpios
40      fields for each of the regulator blocks.
41
42child-binding:
43  include:
44    - name: regulator.yaml
45      property-allowlist:
46        - regulator-always-on
47        - regulator-boot-on
48        - regulator-min-microvolt
49        - regulator-max-microvolt
50        - regulator-init-microvolt
51        - regulator-allowed-modes
52        - regulator-initial-mode
53        - regulator-min-microamp
54        - regulator-max-microamp
55        - regulator-init-microamp
56
57  properties:
58    mode-gpios:
59      type: phandle-array
60      description: |
61        Regulator mode controlled by specified regulator GPIO pin.
62
63    ldosw-wd-reset:
64      type: boolean
65      description: |
66        LDOSW turned off by watchdog reset.
67
68    dps-timer-us:
69      type: int
70      description: |
71        Interval between DPS refresh cycles in microseconds.
72      enum:
73        - 100
74        - 200
75        - 400
76        - 800
77
78    dps-pulse-limit:
79      type: int
80      description: |
81        DPS coil pulse limit per refresh cycle.
82