| /Zephyr-latest/dts/bindings/sdhc/ |
| D | sdhc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 bus: sd
11 max-current-330:
15 Max drive current in mA at 3.3V. A value of zero indicates no maximum
18 max-current-300:
22 Max drive current in mA at 3.0V. A value of zero indicates no maximum
25 max-current-180:
29 Max drive current in mA at 1.8V. A value of zero indicates no maximum
32 max-bus-freq:
36 Maximum bus frequency for SD card. This should be the highest frequency
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| /Zephyr-latest/dts/bindings/mmc/ |
| D | renesas,rcar-emmc.yaml | 1 description: Renesas R-Car eMMC
3 compatible: "renesas,rcar-mmc"
5 include: [sdhc.yaml, mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 max-bus-freq:
23 non-removable:
26 Non-removable slots (like eMMC), which are assumed to always be present,
30 mmc-sdr104-support:
33 cd-gpios:
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| /Zephyr-latest/dts/arm64/renesas/ |
| D | rcar_gen3_ca57.dtsi | 2 * Device Tree Source for the R-Car H3/M3 (R8A77951/R8A77961) SoC
6 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
11 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
23 compatible = "arm,armv8-timer";
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| D | r8a779f0.dtsi | 2 * Device Tree Source for the R-Car S4 (R8A779F0) SoC
6 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
11 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <1>;
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| /Zephyr-latest/dts/bindings/can/ |
| D | microchip,mcp251xfd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The MCP251XFD node is defined on an SPI bus. An example
11 cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;
17 spi-max-frequency = <18000000>;
18 int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
20 osc-freq = <40000000>;
27 include: [spi-device.yaml, can-fd-controller.yaml]
30 osc-freq:
35 int-gpios:
36 type: phandle-array
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| /Zephyr-latest/boards/lilygo/ttgo_lora32/ |
| D | ttgo_lora32_esp32_procpu.dts | 4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "ttgo_lora32-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "lilygo,ttgo-lora32";
19 uart-0 = &uart0;
20 i2c-0 = &i2c0;
29 zephyr,shell-uart = &uart0;
31 zephyr,code-partition = &slot0_partition;
37 compatible = "gpio-leds";
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
27 /* Bus error */
33 /* I2C bus busy */
59 I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE; in i2c_gd32_enable_interrupts()
60 I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE; in i2c_gd32_enable_interrupts()
61 I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE; in i2c_gd32_enable_interrupts()
66 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE; in i2c_gd32_disable_interrupts()
67 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE; in i2c_gd32_disable_interrupts()
68 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE; in i2c_gd32_disable_interrupts()
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| /Zephyr-latest/drivers/timer/ |
| D | stm32_lptim_timer.c | 5 * SPDX-License-Identifier: Apache-2.0
40 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
42 {.bus = STM32_SRC_LSE, .enr = LPTIM1_SEL(3)}
54 * - system clock based on an LPTIM instance, clocked by LSI or LSE
55 * - prescaler is set to a 2^value from 1 (division of the LPTIM source clock by 1)
57 * - using LPTIM AutoReload capability to trig the IRQ (timeout irq)
58 * - when timeout irq occurs the counter is already reset
59 * - the maximum timeout duration is reached with the lptim_time_base value
60 * - with prescaler of 1, the max timeout (LPTIM_TIMEBASE) is 2 seconds:
61 * 0xFFFF / (LSE freq (32768Hz) / 1)
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt6xx_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
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| D | nxp_rt5xx_common.dtsi | 2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
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| D | nxp_rt10xx.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
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| /Zephyr-latest/boards/espressif/esp_wrover_kit/ |
| D | esp_wrover_kit_procpu.dts | 4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "esp_wrover_kit-pinctrl.dtsi"
13 model = "Espressif ESP32-Wrover-Kit PROCPU";
20 pwm-led0 = &pwm_led_red;
21 pwm-led1 = &pwm_led_green;
22 pwm-led2 = &pwm_led_blue;
23 red-pwm-led = &pwm_led_red;
24 green-pwm-led = &pwm_led_green;
25 blue-pwm-led = &pwm_led_blue;
[all …]
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| /Zephyr-latest/dts/x86/intel/ |
| D | alder_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake";
[all …]
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| /Zephyr-latest/drivers/sensor/st/lis2dh/ |
| D | lis2dh.c | 4 * SPDX-License-Identifier: Apache-2.0
23 * Use values for low-power mode in DS "Mechanical (Sensor) characteristics",
39 * maximum converted value we can get is: max(raw_val) * max(scale) in lis2dh_convert()
40 * max(raw_val >> 4) = +/- 2^11 in lis2dh_convert()
41 * max(scale) = 114921 in lis2dh_convert()
42 * max(converted_val) = 235358208 which is less than 2^31 in lis2dh_convert()
45 val->val1 = converted_val / 1000000; in lis2dh_convert()
46 val->val2 = converted_val % 1000000; in lis2dh_convert()
51 int ret = -ENOTSUP; in lis2dh_sample_fetch_temp()
54 struct lis2dh_data *lis2dh = dev->data; in lis2dh_sample_fetch_temp()
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_wba.c | 4 * SPDX-License-Identifier: Apache-2.0
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
96 return -ENOTSUP; in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
[all …]
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \ argument
19 BUILD_ASSERT(val >= min && val <= max, str)
38 "Invalid SCG bus clock divider value");
71 .freq = DT_PROP(SCG_CLOCK_NODE(sosc_clk), clock_frequency),
121 /* System Phase-Locked Loop (SPLL) configuration */
144 .prediv = (SCG_CLOCK_DIV(pll) - 1U),
145 .mult = (SCG_CLOCK_MULT(pll) - 16U)
[all …]
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| /Zephyr-latest/include/zephyr/sd/ |
| D | sd_spec.h | 2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
69 * to inform the SD card the next command is an application-specific one.
87 /* Bits 0-2 reserved */
99 /* Bits 17-18 reserved */
184 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1)
271 /** VDD 2.7-2.8 */
273 /** VDD 2.8-2.9 */
275 /** VDD 2.9-3.0 */
277 /** VDD 3.0-3.1 */
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| /Zephyr-latest/drivers/audio/ |
| D | tlv320dac310x.c | 4 * SPDX-License-Identifier: Apache-2.0
25 #define CODEC_OUTPUT_VOLUME_MIN (-78 * 2)
28 struct i2c_dt_spec bus; member
37 .bus = I2C_DT_SPEC_INST_GET(0),
66 const struct codec_driver_config *const dev_cfg = dev->config; in codec_initialize()
68 if (!device_is_ready(dev_cfg->bus.bus)) { in codec_initialize()
70 return -ENODEV; in codec_initialize()
73 if (!gpio_is_ready_dt(&dev_cfg->reset_gpio)) { in codec_initialize()
75 return -ENODEV; in codec_initialize()
84 const struct codec_driver_config *const dev_cfg = dev->config; in codec_configure()
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| /Zephyr-latest/drivers/sensor/st/lsm6dsv16x/ |
| D | lsm6dsv16x.c | 1 /* ST Microelectronics LSM6DSV16X 6-axis IMU sensor driver
5 * SPDX-License-Identifier: Apache-2.0
29 * should be selected through accel-odr property in DT
48 static int lsm6dsv16x_freq_to_odr_val(const struct device *dev, uint16_t freq) in lsm6dsv16x_freq_to_odr_val() argument
50 const struct lsm6dsv16x_config *cfg = dev->config; in lsm6dsv16x_freq_to_odr_val()
51 stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; in lsm6dsv16x_freq_to_odr_val()
57 return -EINVAL; in lsm6dsv16x_freq_to_odr_val()
63 if (freq <= lsm6dsv16x_odr_map[mode][i]) { in lsm6dsv16x_freq_to_odr_val()
64 LOG_DBG("mode: %d - odr: %d", mode, i); in lsm6dsv16x_freq_to_odr_val()
69 return -EINVAL; in lsm6dsv16x_freq_to_odr_val()
[all …]
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| /Zephyr-latest/boards/nxp/mr_canhubk3/ |
| D | mr_canhubk3.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <freq.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
[all …]
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <freq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
[all …]
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| /Zephyr-latest/boards/nxp/rddrone_fmuk66/ |
| D | rddrone_fmuk66.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include "rddrone_fmuk66-pinctrl.dtsi"
12 #include <freq.h>
21 pwm-led0 = &red_pwm_led;
22 pwm-led1 = &green_pwm_led;
23 pwm-led2 = &blue_pwm_led;
25 red-pwm-led = &red_pwm_led;
26 green-pwm-led = &green_pwm_led;
[all …]
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| /Zephyr-latest/doc/build/dts/ |
| D | howtos.rst | 1 .. _dt-howtos:
6 This page has step-by-step advice for getting things done with devicetree.
8 .. tip:: See :ref:`dt-trouble` for troubleshooting advice.
10 .. _get-devicetree-outputs:
15 A board's devicetree (:ref:`BOARD.dts <devicetree-in-out-files>`) pulls in
26 You can build :zephyr:code-sample:`hello_world` to see the "base" devicetree for your board
27 without any additional changes from :ref:`overlay files <dt-input-files>`.
30 :zephyr:code-sample:`hello_world`:
32 .. code-block:: sh
34 # --cmake-only here just forces CMake to run, skipping the
[all …]
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| /Zephyr-latest/drivers/counter/ |
| D | counter_ll_stm32_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* L0 series MCUs only have 16-bit timers and don't have below macro defined */
94 uint32_t freq; member
118 const struct counter_stm32_config *config = dev->config; in counter_stm32_start()
119 TIM_TypeDef *timer = config->timer; in counter_stm32_start()
129 const struct counter_stm32_config *config = dev->config; in counter_stm32_stop()
130 TIM_TypeDef *timer = config->timer; in counter_stm32_stop()
140 const struct counter_stm32_config *config = dev->config; in counter_stm32_get_top_value()
142 return LL_TIM_GetAutoReload(config->timer); in counter_stm32_get_top_value()
147 const struct counter_stm32_config *config = dev->config; in counter_stm32_read()
[all …]
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_npcx.c | 4 * SPDX-License-Identifier: Apache-2.0
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
118 #define MCLKD_FREQ_MHZ(freq) MHZ(freq) argument
163 uint8_t ppbaud; /* Push-Pull high period */
164 uint8_t pplow; /* Push-Pull low period */
165 uint8_t odhpp; /* Open-Drain high period */
166 uint8_t odbaud; /* Open-Drain low period */
[all …]
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