1/*
2 * Copyright 2020, 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &trng;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			compatible = "arm,cortex-m33f";
27			reg = <0>;
28			cpu-power-states = <&idle &suspend>;
29			#address-cells = <1>;
30			#size-cells = <1>;
31
32			mpu: mpu@e000ed90 {
33				compatible = "arm,armv8m-mpu";
34				reg = <0xe000ed90 0x40>;
35			};
36		};
37
38		power-states {
39			idle: idle {
40				compatible = "zephyr,power-state";
41				power-state-name = "runtime-idle";
42				min-residency-us = <10>;
43			};
44			suspend: suspend {
45				compatible = "zephyr,power-state";
46				power-state-name = "suspend-to-idle";
47				min-residency-us = <1000>;
48			};
49		};
50	};
51};
52
53&sram {
54	#address-cells = <1>;
55	#size-cells = <1>;
56
57	/* RT6XX SRAM partitions are shared
58	 * between code and data. Boards can
59	 * override the reg properties of either sram0 or sram_code nodes to
60	 * change the balance of SRAM allocation.
61	 *
62	 * Note that the sram code region starts at an offset of 0x1B000,
63	 * as the boot ROM will not load code before 0x1C000. The first
64	 * 0x1000 of the image will contain the boot header.
65	 */
66	sram_code: memory@1b000 {
67		compatible = "mmio-sram";
68		reg = <0x1b000 DT_SIZE_K(1428)>;
69	};
70
71	sram0: memory@180000 {
72		compatible = "mmio-sram";
73		reg = <0x180000 DT_SIZE_K(3072)>;
74	};
75
76	sram1: memory@40140000 {
77		compatible =  "zephyr,memory-region", "mmio-sram";
78		reg = <0x40140000 DT_SIZE_K(16)>;
79		zephyr,memory-region = "SRAM1";
80		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
81	};
82};
83
84&systick {
85	/*
86	 * RT600 relies by default on the OS Timer for system clock
87	 * implementation, so the SysTick node is not to be enabled.
88	 */
89	status = "disabled";
90};
91
92&peripheral {
93	#address-cells = <1>;
94	#size-cells = <1>;
95	/*
96	 * Note that the offsets here are relative to the base address
97	 * defined in either nxp_rt6xx_ns.dtsi or nxp_rt6xx.dtsi. The base
98	 * addresses differ between non-secure (0x40000000) and secure
99	 * modes (0x50000000).
100	 */
101
102	flexspi: spi@134000 {
103		reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
104	};
105
106	clkctl0: clkctl@1000 {
107		/* FIXME This chip does NOT have a syscon */
108		compatible = "nxp,lpc-syscon";
109		reg = <0x1000 0x1000>;
110		#clock-cells = <1>;
111	};
112
113	iocon: iocon@4000 {
114		compatible = "nxp,lpc-iocon";
115		reg = <0x4000 0x1000>;
116		pinctrl: pinctrl {
117			compatible = "nxp,rt-iocon-pinctrl";
118		};
119	};
120
121	clkctl1: clkctl@21000 {
122		/* FIXME This chip does NOT have a syscon */
123		compatible = "nxp,lpc-syscon";
124		reg = <0x21000 0x1000>;
125		#clock-cells = <1>;
126	};
127
128	rstctl0: reset@0 {
129		compatible = "nxp,rstctl";
130		reg = <0x0 0x80>;
131		#reset-cells = <1>;
132	};
133
134	rstctl1: reset@20000 {
135		compatible = "nxp,rstctl";
136		reg = <0x20000 0x80>;
137		#reset-cells = <1>;
138	};
139
140	uuid: uuid@2f50 {
141		compatible = "nxp,lpc-uid";
142		reg = <0x2f50 0x10>;
143	};
144
145	gpio: gpio@100000 {
146		compatible = "nxp,lpc-gpio";
147		reg = <0x100000 0x2784>;
148		#address-cells = <1>;
149		#size-cells = <0>;
150
151		gpio0: gpio@0 {
152			compatible = "nxp,lpc-gpio-port";
153			int-source = "pint";
154			gpio-controller;
155			#gpio-cells = <2>;
156			reg = <0>;
157		};
158
159		gpio1: gpio@1 {
160			compatible = "nxp,lpc-gpio-port";
161			int-source = "pint";
162			gpio-controller;
163			#gpio-cells = <2>;
164			reg = <1>;
165		};
166
167		gpio2: gpio@2 {
168			compatible = "nxp,lpc-gpio-port";
169			gpio-controller;
170			#gpio-cells = <2>;
171			reg = <2>;
172		};
173
174		gpio3: gpio@3 {
175			compatible = "nxp,lpc-gpio-port";
176			gpio-controller;
177			#gpio-cells = <2>;
178			reg = <3>;
179		};
180
181		gpio4: gpio@4 {
182			compatible = "nxp,lpc-gpio-port";
183			gpio-controller;
184			#gpio-cells = <2>;
185			reg = <4>;
186		};
187
188		gpio7: gpio@7 {
189			compatible = "nxp,lpc-gpio-port";
190			gpio-controller;
191			#gpio-cells = <2>;
192			reg = <7>;
193		};
194	};
195
196	pint: pint@25000 {
197		compatible = "nxp,pint";
198		reg = <0x25000 0x1000>;
199		interrupt-controller;
200		#interrupt-cells = <1>;
201		#address-cells = <0>;
202		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
203			<35 2>, <36 2>, <37 2>, <38 2>;
204		num-lines = <8>;
205		num-inputs = <64>;
206	};
207
208	flexcomm0: flexcomm@106000 {
209		compatible = "nxp,lpc-flexcomm";
210		reg = <0x106000 0x1000>;
211		interrupts = <14 0>;
212		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
213		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
214		status = "disabled";
215	};
216
217	flexcomm1: flexcomm@107000 {
218		compatible = "nxp,lpc-flexcomm";
219		reg = <0x107000 0x1000>;
220		interrupts = <15 0>;
221		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
222		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
223		status = "disabled";
224	};
225
226	flexcomm2: flexcomm@108000 {
227		compatible = "nxp,lpc-flexcomm";
228		reg = <0x108000 0x1000>;
229		interrupts = <16 0>;
230		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
231		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
232		status = "disabled";
233	};
234
235	flexcomm3: flexcomm@109000 {
236		compatible = "nxp,lpc-flexcomm";
237		reg = <0x109000 0x1000>;
238		interrupts = <17 0>;
239		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
240		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
241		status = "disabled";
242	};
243
244	flexcomm4: flexcomm@122000 {
245		compatible = "nxp,lpc-flexcomm";
246		reg = <0x122000 0x1000>;
247		interrupts = <18 0>;
248		clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>;
249		resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>;
250		status = "disabled";
251	};
252
253	flexcomm5: flexcomm@123000 {
254		compatible = "nxp,lpc-flexcomm";
255		reg = <0x123000 0x1000>;
256		interrupts = <19 0>;
257		clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>;
258		resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>;
259		status = "disabled";
260	};
261
262	flexcomm6: flexcomm@124000 {
263		compatible = "nxp,lpc-flexcomm";
264		reg = <0x124000 0x1000>;
265		interrupts = <43 0>;
266		clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>;
267		resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>;
268		status = "disabled";
269	};
270
271	flexcomm7: flexcomm@125000 {
272		compatible = "nxp,lpc-flexcomm";
273		reg = <0x125000 0x1000>;
274		interrupts = <44 0>;
275		clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>;
276		resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>;
277		status = "disabled";
278	};
279
280	pmic_i2c: i2c@127000 {
281		compatible = "nxp,lpc-i2c";
282		reg = <0x127000 0x1000>;
283		interrupts = <21 0>;
284		clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>;
285		resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>;
286		status = "disabled";
287	};
288
289	usbhs: usbhs@144000 {
290		compatible = "nxp,lpcip3511";
291		reg = <0x144000 0x1000>;
292		interrupts = <50 1>;
293		num-bidir-endpoints = <6>;
294		status = "disabled";
295	};
296
297	usbphy: usbphy@13b000 {
298		compatible = "nxp,usbphy";
299		reg = <0x13b000 0x1000>;
300		status = "disabled";
301	};
302
303	hs_lspi: spi@126000 {
304		compatible = "nxp,lpc-spi";
305		/* Enabling cs-gpios below will allow using GPIO CS,
306		 rather than Flexcomm SS */
307		/* cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
308			<&gpio1 15 GPIO_ACTIVE_LOW>,
309			<&gpio1 16 GPIO_ACTIVE_LOW>,
310			<&gpio1 17 GPIO_ACTIVE_LOW>; */
311		reg = <0x126000 0x1000>;
312		interrupts = <20 0>;
313		clocks = <&clkctl1 MCUX_HS_SPI_CLK>;
314		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
315		status = "disabled";
316		#address-cells = <1>;
317		#size-cells = <0>;
318	};
319
320	dma0: dma-controller@104000 {
321		compatible = "nxp,lpc-dma";
322		reg = <0x104000 0x1000>;
323		interrupts = <1 0>;
324		dma-channels = <33>;
325		status = "disabled";
326		#dma-cells = <1>;
327	};
328
329	dma1: dma-controller@105000 {
330		compatible = "nxp,lpc-dma";
331		reg = <0x105000 0x1000>;
332		interrupts = <54 0>;
333		dma-channels = <33>;
334		status = "disabled";
335		#dma-cells = <1>;
336	};
337
338	dmic0: dmic@121000 {
339		#address-cells = <1>;
340		#size-cells = <0>;
341		compatible = "nxp,dmic";
342		reg = <0x121000 0x1000>;
343		interrupts = <25 0>;
344		status = "disabled";
345		clocks = <&clkctl0 MCUX_DMIC_CLK>;
346
347		pdmc0: dmic-channel@0 {
348			compatible = "nxp,dmic-channel";
349			reg = <0>;
350			dmas = <&dma0 16>;
351			status = "disabled";
352		};
353
354		pdmc1: dmic-channel@1 {
355			compatible = "nxp,dmic-channel";
356			reg = <1>;
357			dmas = <&dma0 17>;
358			status = "disabled";
359		};
360
361		pdmc2: dmic-channel@2 {
362			compatible = "nxp,dmic-channel";
363			reg = <2>;
364			dmas = <&dma0 18>;
365			status = "disabled";
366		};
367
368		pdmc3: dmic-channel@3 {
369			compatible = "nxp,dmic-channel";
370			reg = <3>;
371			dmas = <&dma0 19>;
372			status = "disabled";
373		};
374
375		pdmc4: dmic-channel@4 {
376			compatible = "nxp,dmic-channel";
377			reg = <4>;
378			dmas = <&dma0 20>;
379			status = "disabled";
380		};
381
382		pdmc5: dmic-channel@5 {
383			compatible = "nxp,dmic-channel";
384			reg = <5>;
385			dmas = <&dma0 21>;
386			status = "disabled";
387		};
388
389		pdmc6: dmic-channel@6 {
390			compatible = "nxp,dmic-channel";
391			reg = <6>;
392			dmas = <&dma0 22>;
393			status = "disabled";
394		};
395
396		pdmc7: dmic-channel@7 {
397			compatible = "nxp,dmic-channel";
398			reg = <7>;
399			dmas = <&dma0 23>;
400			status = "disabled";
401		};
402	};
403
404	os_timer: timers@113000 {
405		compatible = "nxp,os-timer";
406		reg = <0x113000 0x1000>;
407		interrupts = <41 0>;
408		status = "disabled";
409	};
410
411	rtc: rtc@30000 {
412		compatible = "nxp,lpc-rtc";
413		reg = <0x30000 0x1000>;
414		interrupts = <32 0>;
415		status = "disabled";
416		rtc_highres: rtc_highres {
417			compatible = "nxp,lpc-rtc-highres";
418			status = "disabled";
419		};
420	};
421
422	trng: random@138000 {
423		compatible = "nxp,kinetis-trng";
424		reg = <0x138000 0x1000>;
425		status = "okay";
426		interrupts = <31 0>;
427	};
428
429	sc_timer: pwm@146000 {
430		compatible = "nxp,sctimer-pwm";
431		reg = <0x146000 0x1000>;
432		interrupts = <12 0>;
433		status = "disabled";
434		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
435		prescaler = <8>;
436		#pwm-cells = <3>;
437	};
438
439	wwdt0: watchdog@e000 {
440		compatible = "nxp,lpc-wwdt";
441		reg = <0xe000 0x1000>;
442		interrupts = <0 0>;
443		status = "disabled";
444		clk-divider = <1>;
445	};
446
447	wwdt1: watchdog@2e000 {
448		compatible = "nxp,lpc-wwdt";
449		reg = <0x2e000 0x1000>;
450		interrupts = <52 0>;
451		status = "disabled";
452		clk-divider = <1>;
453	};
454
455	usdhc0: usdhc@136000 {
456		compatible = "nxp,imx-usdhc";
457		reg = <0x136000 0x1000>;
458		status = "disabled";
459		interrupts = <45 0>;
460		clocks = <&clkctl1 MCUX_USDHC1_CLK>;
461		max-current-330 = <1020>;
462		max-current-180 = <1020>;
463		max-bus-freq = <208000000>;
464		min-bus-freq = <400000>;
465	};
466
467	usdhc1: usdhc@137000 {
468		compatible = "nxp,imx-usdhc";
469		reg = <0x137000 0x1000>;
470		status = "disabled";
471		interrupts = <46 0>;
472		clocks = <&clkctl1 MCUX_USDHC2_CLK>;
473		max-current-330 = <1020>;
474		max-current-180 = <1020>;
475		max-bus-freq = <208000000>;
476		min-bus-freq = <400000>;
477	};
478
479	lpadc0: adc@13a000 {
480		compatible = "nxp,lpc-lpadc";
481		reg = <0x13a000 0x304>;
482		interrupts = <22 0>;
483		status = "disabled";
484		clk-divider = <1>;
485		clk-source = <0>;
486		voltage-ref= <1>;
487		calibration-average = <128>;
488		power-level = <0>;
489		offset-value-a = <10>;
490		offset-value-b = <10>;
491		#io-channel-cells = <1>;
492		clocks = <&clkctl1 MCUX_LPADC1_CLK>;
493	};
494
495	ctimer0: ctimer@28000 {
496		compatible = "nxp,lpc-ctimer";
497		reg = <0x28000 0x1000>;
498		interrupts = <10 0>;
499		status = "disabled";
500		clk-source = <1>;
501		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
502		mode = <0>;
503		input = <0>;
504		prescale = <0>;
505	};
506
507	ctimer1: ctimer@29000 {
508		compatible = "nxp,lpc-ctimer";
509		reg = <0x29000 0x1000>;
510		interrupts = <11 0>;
511		status = "disabled";
512		clk-source = <1>;
513		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
514		mode = <0>;
515		input = <0>;
516		prescale = <0>;
517	};
518
519	ctimer2: ctimer@2a000 {
520		compatible = "nxp,lpc-ctimer";
521		reg = <0x2a000 0x1000>;
522		interrupts = <39 0>;
523		status = "disabled";
524		clk-source = <1>;
525		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
526		mode = <0>;
527		input = <0>;
528		prescale = <0>;
529	};
530
531	ctimer3: ctimer@2b000 {
532		compatible = "nxp,lpc-ctimer";
533		reg = <0x2b000 0x1000>;
534		interrupts = <13 0>;
535		status = "disabled";
536		clk-source = <1>;
537		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
538		mode = <0>;
539		input = <0>;
540		prescale = <0>;
541	};
542
543	ctimer4: ctimer@2c000 {
544		compatible = "nxp,lpc-ctimer";
545		reg = <0x2c000 0x1000>;
546		interrupts = <40 0>;
547		status = "disabled";
548		clk-source = <1>;
549		clocks = <&clkctl1 MCUX_CTIMER4_CLK>;
550		mode = <0>;
551		input = <0>;
552		prescale = <0>;
553	};
554
555	i3c0: i3c@36000 {
556		compatible = "nxp,mcux-i3c";
557		reg = <0x36000 0x1000>;
558		interrupts = <49 0>;
559		clocks = <&clkctl1 MCUX_I3C_CLK>;
560		clk-divider = <2>;
561		clk-divider-slow = <1>;
562		clk-divider-tc = <1>;
563		status = "disabled";
564		#address-cells = <3>;
565		#size-cells = <0>;
566	};
567
568	mrt: mrt@2d000 {
569		compatible = "nxp,mrt";
570		reg = <0x2d000 0x100>;
571		interrupts = <9 0>;
572		num-channels = <4>;
573		num-bits = <24>;
574		clocks = <&clkctl1 MCUX_MRT_CLK>;
575		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
576		#address-cells = <1>;
577		#size-cells = <0>;
578
579		mrt_channel0: mrt_channel@0 {
580			compatible = "nxp,mrt-channel";
581			reg = <0>;
582			status = "disabled";
583		};
584		mrt_channel1: mrt_channel@1 {
585			compatible = "nxp,mrt-channel";
586			reg = <1>;
587			status = "disabled";
588		};
589		mrt_channel2: mrt_channel@2 {
590			compatible = "nxp,mrt-channel";
591			reg = <2>;
592			status = "disabled";
593		};
594		mrt_channel3: mrt_channel@3 {
595			compatible = "nxp,mrt-channel";
596			reg = <3>;
597			status = "disabled";
598		};
599	};
600};
601
602&flexspi {
603	compatible = "nxp,imx-flexspi";
604	interrupts = <42 0>;
605	#address-cells = <1>;
606	#size-cells = <0>;
607	status = "disabled";
608	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
609};
610
611&nvic {
612	arm,num-irq-priority-bits = <3>;
613};
614