Lines Matching +full:max +full:- +full:bus +full:- +full:freq
2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \ argument
19 BUILD_ASSERT(val >= min && val <= max, str)
38 "Invalid SCG bus clock divider value");
71 .freq = DT_PROP(SCG_CLOCK_NODE(sosc_clk), clock_frequency),
121 /* System Phase-Locked Loop (SPLL) configuration */
144 .prediv = (SCG_CLOCK_DIV(pll) - 1U),
145 .mult = (SCG_CLOCK_MULT(pll) - 16U)
161 CLOCK_SetXtal0Freq(scg_sosc_config.freq); in clk_init()
250 * Note that the KE1xF does not implement the optional ARMv7-M memory in soc_early_init_hook()
252 * Cortex-M4 core. Instead, the processor includes its own MPU module. in soc_early_init_hook()
254 temp_reg = SYSMPU->CESR; in soc_early_init_hook()
257 SYSMPU->CESR = temp_reg; in soc_early_init_hook()
277 * reconfiguration must take place within 128 bus clocks from in z_arm_watchdog_init()
288 WDOG->CNT = WDOG_UPDATE_KEY; in z_arm_watchdog_init()
289 while (!(WDOG->CS & WDOG_CS_ULK_MASK)) { in z_arm_watchdog_init()
297 WDOG->TOVAL = CONFIG_WDOG_INITIAL_TIMEOUT >> 1; in z_arm_watchdog_init()
298 WDOG->CS = WDOG_CS_PRES(1) | WDOG_CS_CLK(1) | WDOG_CS_WAIT(1) | in z_arm_watchdog_init()
301 while (!(WDOG->CS & WDOG_CS_RCS_MASK)) { in z_arm_watchdog_init()