1/*
2 * Device Tree Source for the R-Car S4 (R8A779F0) SoC
3 *
4 * Copyright (C) 2023 EPAM Systems.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8#include <arm64/armv8-a.dtsi>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
11#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
12
13/ {
14	compatible = "renesas,r8a779f0";
15	#address-cells = <2>;
16	#size-cells = <2>;
17	interrupt-parent = <&gic>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		a55: cpu@0 {
24			compatible = "arm,armv8";
25			reg = <0>;
26			device_type = "cpu";
27			enable-method = "psci";
28		};
29	};
30
31	psci {
32		compatible = "arm,psci-0.2";
33		method = "smc";
34	};
35
36	arch_timer: timer {
37		compatible = "arm,armv8-timer";
38		interrupt-parent = <&gic>;
39		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
40			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
41			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
42			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
43	};
44
45	reg_3p3v: regulator_3p3v {
46		compatible = "regulator-fixed";
47		regulator-name = "reg_3p3v";
48		regulator-min-microvolt = <3300000>;
49		regulator-max-microvolt = <3300000>;
50		regulator-always-on;
51		regulator-boot-on;
52		status = "okay";
53	};
54
55	reg_1p8v: regulator_1p8v {
56		compatible = "regulator-fixed";
57		regulator-name = "reg_1p8v";
58		regulator-min-microvolt = <1800000>;
59		regulator-max-microvolt = <1800000>;
60		regulator-always-on;
61		regulator-boot-on;
62		status = "okay";
63	};
64
65	soc: soc {
66		compatible = "simple-bus";
67		interrupt-parent = <&gic>;
68
69		#address-cells = <2>;
70		#size-cells = <2>;
71		ranges;
72
73		gic: interrupt-controller@f1000000 {
74			compatible = "arm,gic-600", "arm,gic-v3", "arm,gic";
75			#interrupt-cells = <4>;
76			#address-cells = <0>;
77			interrupt-controller;
78			reg = <0 0xf1000000 0 0x20000>,
79			      <0 0xf1060000 0 0x110000>;
80			status = "okay";
81		};
82
83		cpg: clock-controller@e6150000 {
84			compatible = "renesas,r8a779f0-cpg-mssr";
85			reg = <0 0xe6150000 0 0x4000>;
86			#clock-cells = <2>;
87			#power-domain-cells = <0>;
88			#reset-cells = <1>;
89		};
90
91		mmc0: mmc@ee140000 {
92			compatible = "renesas,rcar-mmc";
93			reg = <0 0xee140000 0 0x2000>;
94			vmmc-supply = <&reg_3p3v>;
95			vqmmc-supply = <&reg_1p8v>;
96			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
97			clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
98			max-bus-freq = <200000000>;
99			status = "disabled";
100		};
101
102		pfc: pin-controller@e6050000 {
103			compatible = "renesas,rcar-pfc";
104			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
105			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
106			      <0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>,
107			      <0 0xdfd91000 0 0x16c>, <0 0xdfd91800 0 0x16c>;
108		};
109
110		hscif0: serial@e6540000 {
111			compatible = "renesas,rcar-hscif";
112			reg = <0 0xe6540000 0 0x60>;
113			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
114			clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>;
115			status = "disabled";
116		};
117	};
118};
119