1/* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8#include <arm/nxp/nxp_s32k344_m7.dtsi> 9#include <dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/input/input-event-codes.h> 11#include <freq.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "mr_canhubk3-pinctrl.dtsi" 14#include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h> 15 16/ { 17 model = "NXP MR-CANHUBK3"; 18 compatible = "nxp,mr_canhubk3"; 19 20 chosen { 21 zephyr,sram = &sram0_1; 22 zephyr,flash = &flash0; 23 zephyr,itcm = &itcm; 24 zephyr,dtcm = &dtcm; 25 zephyr,code-partition = &code_partition; 26 zephyr,console = &lpuart2; 27 zephyr,shell-uart = &lpuart2; 28 zephyr,flash-controller = &mx25l6433f; 29 zephyr,canbus = &flexcan0; 30 zephyr,display = &ssd1306; 31 }; 32 33 aliases { 34 dma0 = &edma0; 35 led0 = &user_led1_red; 36 led1 = &user_led1_green; 37 led2 = &user_led1_blue; 38 sw0 = &user_button_1; 39 sw1 = &user_button_2; 40 watchdog0 = &swt0; 41 /* For pwm test suites */ 42 pwm-0 = &emios0_pwm; 43 pwm-1 = &flexio0_pwm; 44 red-pwm-led = &user_led1_red_pwm; 45 green-pwm-led = &user_led1_green_pwm; 46 blue-pwm-led = &user_led1_blue_pwm; 47 pwm-led0 = &user_led1_blue_pwm; 48 qdec0 = &qdec0; 49 }; 50 51 leds { 52 compatible = "gpio-leds"; 53 user_led1_green: user_led1_green { 54 gpios = <&gpioa_h 11 GPIO_ACTIVE_LOW>; 55 label = "User RGB LED1 GREEN"; 56 }; 57 user_led1_blue: user_led1_blue { 58 gpios = <&gpioe_l 12 GPIO_ACTIVE_LOW>; 59 label = "User RGB LED1 BLUE"; 60 }; 61 user_led1_red: user_led1_red { 62 gpios = <&gpioe_l 14 GPIO_ACTIVE_LOW>; 63 label = "User RGB LED1 RED"; 64 }; 65 can_led0: can_led0 { 66 gpios = <&gpioc_h 2 GPIO_ACTIVE_LOW>; 67 label = "CAN LED0"; 68 }; 69 can_led1: can_led1 { 70 gpios = <&gpioe_l 5 GPIO_ACTIVE_LOW>; 71 label = "CAN LED1"; 72 }; 73 can_led2: can_led2 { 74 gpios = <&gpiod_h 4 GPIO_ACTIVE_LOW>; 75 label = "CAN LED2"; 76 }; 77 can_led3: can_led3 { 78 gpios = <&gpiob_h 8 GPIO_ACTIVE_LOW>; 79 label = "CAN LED3"; 80 }; 81 can_led4: can_led4 { 82 gpios = <&gpiob_h 10 GPIO_ACTIVE_LOW>; 83 label = "CAN LED4"; 84 }; 85 can_led5: can_led5 { 86 gpios = <&gpiod_h 15 GPIO_ACTIVE_LOW>; 87 label = "CAN LED5"; 88 }; 89 }; 90 91 /* gpio-leds and pwm-leds are the same RGB LED and cannot be used at the same time. */ 92 pwmleds { 93 compatible = "pwm-leds"; 94 95 user_led1_blue_pwm: user_led1_blue { 96 pwms = <&emios1_pwm 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>; 97 }; 98 99 user_led1_green_pwm: user_led1_green { 100 pwms = <&emios1_pwm 10 PWM_MSEC(20) PWM_POLARITY_INVERTED>; 101 }; 102 103 user_led1_red_pwm: user_led1_red { 104 pwms = <&emios0_pwm 19 PWM_MSEC(20) PWM_POLARITY_INVERTED>; 105 }; 106 }; 107 108 qdec0: qdec0 { 109 compatible = "nxp,qdec-s32"; 110 pinctrl-0 = <&qdec_s32>; 111 pinctrl-names = "default"; 112 micro-ticks-per-rev = <685440000>; 113 status = "okay"; 114 trgmux = <&trgmux>; 115 trgmux-io-config = 116 <0 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2>, 117 <1 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3>, 118 <2 TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 TRGMUX_IP_INPUT_SIUL2_IN2>, 119 <3 TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 TRGMUX_IP_INPUT_SIUL2_IN3>; 120 lcu = <&lcu1>; 121 lcu-input-idx = 122 <LCU_IP_IN_0 LCU_IP_IN_1 123 LCU_IP_IN_2 LCU_IP_IN_3>; 124 lcu-mux-sel = 125 <LCU_IP_MUX_SEL_LU_IN_0 LCU_IP_MUX_SEL_LU_IN_1 126 LCU_IP_MUX_SEL_LU_OUT_0 LCU_IP_MUX_SEL_LU_OUT_1>; 127 lcu-output-filter-config = 128 /* LCU Out HW ID, Rise Filter, Fall Filter */ 129 <0 5 5>, /* LCU O0 */ 130 <1 5 5>, /* LCU O1 */ 131 <2 2 2>, /* LCU O2 */ 132 <3 2 2>; /* LCU O3 */ 133 emios = <&emios0>; 134 /* 135 * eMios channel numbers for qdec should be beyond the channel numbers 136 * used by the emios pwm 137 */ 138 emios-channels = <6 7>; 139 }; 140 141 gpio_keys { 142 compatible = "gpio-keys"; 143 user_button_1: button_0 { 144 label = "User SW1"; 145 gpios = <&gpiod_l 15 GPIO_ACTIVE_HIGH>; 146 zephyr,code = <INPUT_KEY_0>; 147 }; 148 user_button_2: button_1 { 149 label = "User SW2"; 150 gpios = <&gpioa_h 9 GPIO_ACTIVE_HIGH>; 151 zephyr,code = <INPUT_KEY_1>; 152 }; 153 }; 154 155 can_phy0: can-phy0 { 156 compatible = "nxp,tja1443", "can-transceiver-gpio"; 157 enable-gpios = <&gpioc_h 8 GPIO_ACTIVE_HIGH>; 158 standby-gpios = <&gpioc_h 5 GPIO_ACTIVE_LOW>; 159 max-bitrate = <5000000>; 160 #phy-cells = <0>; 161 }; 162 163 can_phy1: can-phy1 { 164 compatible = "nxp,tja1443", "can-transceiver-gpio"; 165 enable-gpios = <&gpiod_l 2 GPIO_ACTIVE_HIGH>; 166 standby-gpios = <&gpiod_h 7 GPIO_ACTIVE_LOW>; 167 max-bitrate = <5000000>; 168 #phy-cells = <0>; 169 }; 170 171 can_phy2: can-phy2 { 172 compatible = "nxp,tja1463", "can-transceiver-gpio"; 173 enable-gpios = <&gpiod_l 4 GPIO_ACTIVE_HIGH>; 174 standby-gpios = <&gpiod_h 6 GPIO_ACTIVE_LOW>; 175 max-bitrate = <8000000>; 176 #phy-cells = <0>; 177 }; 178 179 can_phy3: can-phy3 { 180 compatible = "nxp,tja1463", "can-transceiver-gpio"; 181 enable-gpios = <&gpiob_l 0 GPIO_ACTIVE_HIGH>; 182 standby-gpios = <&gpiob_l 1 GPIO_ACTIVE_LOW>; 183 max-bitrate = <8000000>; 184 #phy-cells = <0>; 185 }; 186 187 can_phy4: can-phy4 { 188 compatible = "nxp,tja1153", "can-transceiver-gpio"; 189 enable-gpios = <&gpioc_h 10 GPIO_ACTIVE_HIGH>; 190 standby-gpios = <&gpioc_h 9 GPIO_ACTIVE_LOW>; 191 max-bitrate = <2000000>; 192 #phy-cells = <0>; 193 }; 194 195 can_phy5: can-phy5 { 196 compatible = "nxp,tja1153", "can-transceiver-gpio"; 197 enable-gpios = <&gpioe_h 1 GPIO_ACTIVE_HIGH>; 198 standby-gpios = <&gpiod_h 14 GPIO_ACTIVE_LOW>; 199 max-bitrate = <2000000>; 200 #phy-cells = <0>; 201 }; 202}; 203 204&pmc { 205 lm-reg; 206}; 207 208&flash0 { 209 partitions { 210 compatible = "fixed-partitions"; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 214 ivt_header: partition@0 { 215 label = "ivt-header"; 216 reg = <0x00000000 0x100>; 217 }; 218 219 code_partition: partition@100 { 220 label = "code-partition"; 221 reg = <0x00000100 (DT_SIZE_K(4048) - 0x100)>; 222 }; 223 }; 224}; 225 226&gpioa_h { 227 status = "okay"; 228}; 229 230&gpioe_l { 231 status = "okay"; 232}; 233 234/* Enable gpio to control the CAN transceivers and LEDs */ 235 236&gpiob_h { 237 status = "okay"; 238}; 239 240&gpioc_h { 241 status = "okay"; 242}; 243 244&gpiod_l { 245 status = "okay"; 246}; 247 248&gpiod_h { 249 status = "okay"; 250}; 251 252&gpiob_l { 253 status = "okay"; 254}; 255 256&gpioe_h { 257 status = "okay"; 258}; 259 260&eirq0 { 261 pinctrl-0 = <&eirq0_default>; 262 pinctrl-names = "default"; 263 status = "okay"; 264}; 265 266&lpuart0 { 267 pinctrl-0 = <&lpuart0_default>; 268 pinctrl-names = "default"; 269 dmas = <&edma0 0 37>, <&edma0 1 38>; 270 dma-names = "tx", "rx"; 271}; 272 273&lpuart1 { 274 pinctrl-0 = <&lpuart1_default>; 275 pinctrl-names = "default"; 276 dmas = <&edma0 2 39>, <&edma0 3 40>; 277 dma-names = "tx", "rx"; 278}; 279 280&lpuart2 { 281 pinctrl-0 = <&lpuart2_default>; 282 pinctrl-names = "default"; 283 current-speed = <115200>; 284 dmas = <&edma0 16 38>, <&edma0 17 39>; 285 dma-names = "tx", "rx"; 286 status = "okay"; 287}; 288 289&lpuart9 { 290 pinctrl-0 = <&lpuart9_default>; 291 pinctrl-names = "default"; 292 /* 293 * LPUART 1 and 9 share the same DMA source for TX 294 * and RX, using UART async API for both instances 295 * should be careful. 296 */ 297 dmas = <&edma0 4 39>, <&edma0 5 40>; 298 dma-names = "tx", "rx"; 299}; 300 301&lpuart10 { 302 pinctrl-0 = <&lpuart10_default>; 303 pinctrl-names = "default"; 304 /* 305 * LPUART 2 and 10 share the same DMA source for TX 306 * and RX, using UART async API for both instances 307 * should be careful. 308 */ 309 dmas = <&edma0 18 38>, <&edma0 19 39>; 310 dma-names = "tx", "rx"; 311}; 312 313&lpuart13 { 314 pinctrl-0 = <&lpuart13_default>; 315 pinctrl-names = "default"; 316 dmas = <&edma0 20 44>, <&edma0 21 45>; 317 dma-names = "tx", "rx"; 318}; 319 320&lpuart14 { 321 pinctrl-0 = <&lpuart14_default>; 322 pinctrl-names = "default"; 323 dmas = <&edma0 22 46>, <&edma0 23 47>; 324 dma-names = "tx", "rx"; 325}; 326 327&qspi0 { 328 pinctrl-0 = <&qspi0_default>; 329 pinctrl-names = "default"; 330 data-rate = "SDR"; 331 a-rx-clock-source = "LOOPBACK"; 332 a-dll-mode = "BYPASSED"; 333 ahb-buffers-masters = <0 1 2 3>; 334 ahb-buffers-sizes = <0 0 0 256>; 335 ahb-buffers-all-masters; 336 status = "okay"; 337 338 mx25l6433f: mx25l6433f@0 { 339 compatible = "nxp,s32-qspi-nor"; 340 reg = <0>; 341 size = <DT_SIZE_M(64)>; 342 jedec-id = [c2 20 17]; 343 quad-enable-requirements = "S1B6"; 344 readoc = "1-4-4"; 345 writeoc = "1-4-4"; 346 has-32k-erase; 347 status = "okay"; 348 349 partitions { 350 compatible = "fixed-partitions"; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 354 storage_partition: partition@0 { 355 label = "storage"; 356 reg = <0x0 0x100000>; 357 }; 358 }; 359 }; 360}; 361 362&flexcan0 { 363 pinctrl-0 = <&flexcan0_default>; 364 pinctrl-names = "default"; 365 phys = <&can_phy0>; 366 status = "okay"; 367}; 368 369&flexcan1 { 370 pinctrl-0 = <&flexcan1_default>; 371 pinctrl-names = "default"; 372 phys = <&can_phy1>; 373}; 374 375&flexcan2 { 376 pinctrl-0 = <&flexcan2_default>; 377 pinctrl-names = "default"; 378 phys = <&can_phy2>; 379}; 380 381&flexcan3 { 382 pinctrl-0 = <&flexcan3_default>; 383 pinctrl-names = "default"; 384 phys = <&can_phy3>; 385}; 386 387&flexcan4 { 388 pinctrl-0 = <&flexcan4_default>; 389 pinctrl-names = "default"; 390 phys = <&can_phy4>; 391}; 392 393&flexcan5 { 394 pinctrl-0 = <&flexcan5_default>; 395 pinctrl-names = "default"; 396 phys = <&can_phy5>; 397}; 398 399&lpi2c0 { 400 pinctrl-0 = <&lpi2c0_default>; 401 pinctrl-names = "default"; 402 clock-frequency = <I2C_BITRATE_STANDARD>; 403 status = "okay"; 404 405 ssd1306: ssd1306@3c { 406 compatible = "solomon,ssd1306fb"; 407 reg = <0x3c>; 408 width = <128>; 409 height = <32>; 410 segment-offset = <0>; 411 page-offset = <0>; 412 display-offset = <0>; 413 multiplex-ratio = <31>; 414 segment-remap; 415 com-invdir; 416 com-sequential; 417 prechargep = <0x22>; 418 }; 419}; 420 421&lpi2c1 { 422 pinctrl-0 = <&lpi2c1_default>; 423 pinctrl-names = "default"; 424 clock-frequency = <I2C_BITRATE_STANDARD>; 425}; 426 427&lpspi1 { 428 pinctrl-0 = <&lpspi1_default>; 429 pinctrl-names = "default"; 430 data-pin-config = "sdo-in,sdi-out"; 431}; 432 433&lpspi2 { 434 pinctrl-0 = <&lpspi2_default>; 435 pinctrl-names = "default"; 436 data-pin-config = "sdo-in,sdi-out"; 437}; 438 439&lpspi3 { 440 pinctrl-0 = <&lpspi3_default>; 441 pinctrl-names = "default"; 442 data-pin-config = "sdo-in,sdi-out"; 443 status = "okay"; 444 445 fs26_wdt: watchdog@0 { 446 compatible = "nxp,fs26-wdog"; 447 reg = <0>; 448 spi-max-frequency = <DT_FREQ_M(5)>; 449 type = "challenger"; 450 int-gpios = <&gpioa_h 2 GPIO_ACTIVE_LOW>; 451 status = "okay"; 452 }; 453}; 454 455&lpspi4 { 456 pinctrl-0 = <&lpspi4_default>; 457 pinctrl-names = "default"; 458 data-pin-config = "sdo-in,sdi-out"; 459}; 460 461&lpspi5 { 462 pinctrl-0 = <&lpspi5_default>; 463 pinctrl-names = "default"; 464 data-pin-config = "sdo-in,sdi-out"; 465}; 466 467&emac0 { 468 pinctrl-0 = <&emac0_default>; 469 pinctrl-names = "default"; 470 phy-connection-type = "rmii"; 471 local-mac-address = [02 04 9f aa bb cc]; 472 phy-handle = <&phy>; 473 status = "okay"; 474}; 475 476&mdio0 { 477 pinctrl-0 = <&mdio0_default>; 478 pinctrl-names = "default"; 479 status = "okay"; 480 481 phy: ethernet-phy@12 { 482 compatible = "nxp,tja1103"; 483 status = "okay"; 484 reg = <0x12>; 485 int-gpios = <&gpiod_l 5 GPIO_ACTIVE_LOW>; 486 master-slave = "slave"; 487 }; 488}; 489 490&emios0 { 491 clock-divider = <200>; 492 status = "okay"; 493 494 master_bus { 495 /* 496 * Timebase for PWM led, setting clock 50KHz for internal counter, 497 * default period is 1000 cycles <-> 20ms. 498 */ 499 emios0_bus_a { 500 mode = "MCB_UP_COUNTER"; 501 prescaler = <16>; 502 period = <1000>; 503 status = "okay"; 504 }; 505 }; 506 507 emios0_pwm: pwm { 508 pinctrl-0 = <&emios0_default>; 509 pinctrl-names = "default"; 510 status = "okay"; 511 512 /* Default clock for internal counter for PWM channel 0-7 is 100Khz */ 513 pwm_0 { 514 channel = <0>; 515 pwm-mode = "OPWFMB"; 516 period = <65535>; 517 duty-cycle = <0>; 518 prescaler = <8>; 519 polarity = "ACTIVE_HIGH"; 520 }; 521 522 pwm_1 { 523 channel = <1>; 524 pwm-mode = "OPWFMB"; 525 period = <65535>; 526 duty-cycle = <0>; 527 prescaler = <8>; 528 polarity = "ACTIVE_HIGH"; 529 }; 530 531 pwm_2 { 532 channel = <2>; 533 pwm-mode = "OPWFMB"; 534 period = <65535>; 535 duty-cycle = <0>; 536 prescaler = <8>; 537 polarity = "ACTIVE_HIGH"; 538 }; 539 540 pwm_3 { 541 channel = <3>; 542 pwm-mode = "OPWFMB"; 543 period = <65535>; 544 duty-cycle = <0>; 545 prescaler = <8>; 546 polarity = "ACTIVE_HIGH"; 547 }; 548 549 pwm_4 { 550 channel = <4>; 551 pwm-mode = "OPWFMB"; 552 period = <65535>; 553 duty-cycle = <0>; 554 prescaler = <8>; 555 polarity = "ACTIVE_HIGH"; 556 }; 557 558 pwm_5 { 559 channel = <5>; 560 pwm-mode = "OPWFMB"; 561 period = <65535>; 562 duty-cycle = <0>; 563 prescaler = <8>; 564 polarity = "ACTIVE_HIGH"; 565 }; 566 567 rgb_red { 568 channel = <19>; 569 master-bus = <&emios0_bus_a>; 570 duty-cycle = <0>; 571 pwm-mode = "OPWMB"; 572 polarity = "ACTIVE_LOW"; 573 }; 574 }; 575}; 576 577&emios1 { 578 clock-divider = <200>; 579 status = "okay"; 580 581 master_bus { 582 /* 583 * Timebase for PWM led, setting clock 50KHz for internal counter, 584 * default period is 1000 cycles <-> 20ms. 585 */ 586 emios1_bus_a { 587 prescaler = <16>; 588 mode = "MCB_UP_COUNTER"; 589 period = <1000>; 590 status = "okay"; 591 }; 592 593 emios1_bus_f { 594 prescaler = <16>; 595 mode = "MCB_UP_COUNTER"; 596 period = <1000>; 597 status = "okay"; 598 }; 599 }; 600 601 emios1_pwm: pwm { 602 pinctrl-0 = <&emios1_default>; 603 pinctrl-names = "default"; 604 status = "okay"; 605 606 rgb_green { 607 channel = <10>; 608 master-bus = <&emios1_bus_a>; 609 duty-cycle = <0>; 610 pwm-mode = "OPWMB"; 611 polarity = "ACTIVE_LOW"; 612 }; 613 614 rgb_blue { 615 channel = <5>; 616 master-bus = <&emios1_bus_f>; 617 duty-cycle = <0>; 618 pwm-mode = "OPWMB"; 619 polarity = "ACTIVE_LOW"; 620 }; 621 }; 622}; 623 624&flexio0 { 625 status = "okay"; 626 627 flexio0_pwm: flexio0_pwm { 628 pinctrl-0 = <&flexio0_pwm_default>; 629 pinctrl-names = "default"; 630 status = "okay"; 631 632 pwm_0 { 633 pin-id = <19>; 634 prescaler = <1>; 635 }; 636 637 pwm_1 { 638 pin-id = <11>; 639 prescaler = <1>; 640 }; 641 }; 642 643}; 644 645&lcu1 { 646 status = "okay"; 647}; 648 649&trgmux { 650 status = "okay"; 651}; 652 653&edma0 { 654 status = "okay"; 655}; 656
