1 /*
2 * Copyright (c) 2021 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT gd_gd32_i2c
8
9 #include <errno.h>
10
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/gd32.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/devicetree.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/drivers/reset.h>
17 #include <zephyr/drivers/i2c.h>
18
19 #include <gd32_i2c.h>
20
21 #include <zephyr/logging/log.h>
22 #include <zephyr/irq.h>
23 LOG_MODULE_REGISTER(i2c_gd32, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 /* Bus error */
28 #define I2C_GD32_ERR_BERR BIT(0)
29 /* Arbitration lost */
30 #define I2C_GD32_ERR_LARB BIT(1)
31 /* No ACK received */
32 #define I2C_GD32_ERR_AERR BIT(2)
33 /* I2C bus busy */
34 #define I2C_GD32_ERR_BUSY BIT(4)
35
36 struct i2c_gd32_config {
37 uint32_t reg;
38 uint32_t bitrate;
39 uint16_t clkid;
40 struct reset_dt_spec reset;
41 const struct pinctrl_dev_config *pcfg;
42 void (*irq_cfg_func)(void);
43 };
44
45 struct i2c_gd32_data {
46 struct k_sem bus_mutex;
47 struct k_sem sync_sem;
48 uint32_t dev_config;
49 uint16_t addr1;
50 uint16_t addr2;
51 uint32_t xfer_len;
52 struct i2c_msg *current;
53 uint8_t errs;
54 bool is_restart;
55 };
56
i2c_gd32_enable_interrupts(const struct i2c_gd32_config * cfg)57 static inline void i2c_gd32_enable_interrupts(const struct i2c_gd32_config *cfg)
58 {
59 I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE;
60 I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE;
61 I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE;
62 }
63
i2c_gd32_disable_interrupts(const struct i2c_gd32_config * cfg)64 static inline void i2c_gd32_disable_interrupts(const struct i2c_gd32_config *cfg)
65 {
66 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE;
67 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE;
68 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
69 }
70
i2c_gd32_xfer_read(struct i2c_gd32_data * data,const struct i2c_gd32_config * cfg)71 static inline void i2c_gd32_xfer_read(struct i2c_gd32_data *data,
72 const struct i2c_gd32_config *cfg)
73 {
74 data->current->len--;
75 *data->current->buf = I2C_DATA(cfg->reg);
76 data->current->buf++;
77
78 if ((data->xfer_len > 0U) &&
79 (data->current->len == 0U)) {
80 data->current++;
81 }
82 }
83
i2c_gd32_xfer_write(struct i2c_gd32_data * data,const struct i2c_gd32_config * cfg)84 static inline void i2c_gd32_xfer_write(struct i2c_gd32_data *data,
85 const struct i2c_gd32_config *cfg)
86 {
87 data->current->len--;
88 I2C_DATA(cfg->reg) = *data->current->buf;
89 data->current->buf++;
90
91 if ((data->xfer_len > 0U) &&
92 (data->current->len == 0U)) {
93 data->current++;
94 }
95 }
96
i2c_gd32_handle_rbne(const struct device * dev)97 static void i2c_gd32_handle_rbne(const struct device *dev)
98 {
99 struct i2c_gd32_data *data = dev->data;
100 const struct i2c_gd32_config *cfg = dev->config;
101
102 switch (data->xfer_len) {
103 case 0:
104 /* Unwanted data received, ignore it. */
105 k_sem_give(&data->sync_sem);
106 break;
107 case 1:
108 /* If total_read_length == 1, read the data directly. */
109 data->xfer_len--;
110 i2c_gd32_xfer_read(data, cfg);
111
112 k_sem_give(&data->sync_sem);
113
114 break;
115 case 2:
116 __fallthrough;
117 case 3:
118 /*
119 * If total_read_length == 2, or total_read_length > 3
120 * and remaining_read_length == 3, disable the RBNE
121 * interrupt.
122 * Remaining data will be read from BTC interrupt.
123 */
124 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
125 break;
126 default:
127 /*
128 * If total_read_length > 3 and remaining_read_length > 3,
129 * read the data directly.
130 */
131 data->xfer_len--;
132 i2c_gd32_xfer_read(data, cfg);
133 break;
134 }
135
136 }
137
i2c_gd32_handle_tbe(const struct device * dev)138 static void i2c_gd32_handle_tbe(const struct device *dev)
139 {
140 struct i2c_gd32_data *data = dev->data;
141 const struct i2c_gd32_config *cfg = dev->config;
142
143 if (data->xfer_len > 0U) {
144 data->xfer_len--;
145 if (data->xfer_len == 0U) {
146 /*
147 * This is the last data to transmit, disable the TBE interrupt.
148 * Use the BTC interrupt to indicate the write data complete state.
149 */
150 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
151 }
152 i2c_gd32_xfer_write(data, cfg);
153
154 } else {
155 /* Enter stop condition */
156 I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
157
158 k_sem_give(&data->sync_sem);
159 }
160 }
161
i2c_gd32_handle_btc(const struct device * dev)162 static void i2c_gd32_handle_btc(const struct device *dev)
163 {
164 struct i2c_gd32_data *data = dev->data;
165 const struct i2c_gd32_config *cfg = dev->config;
166
167 if (data->current->flags & I2C_MSG_READ) {
168 uint32_t counter = 0U;
169
170 switch (data->xfer_len) {
171 case 2:
172 /* Stop condition must be generated before reading the last two bytes. */
173 I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
174
175 for (counter = 2U; counter > 0; counter--) {
176 data->xfer_len--;
177 i2c_gd32_xfer_read(data, cfg);
178 }
179
180 k_sem_give(&data->sync_sem);
181
182 break;
183 case 3:
184 /* Clear ACKEN bit */
185 I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
186
187 data->xfer_len--;
188 i2c_gd32_xfer_read(data, cfg);
189
190 break;
191 default:
192 i2c_gd32_handle_rbne(dev);
193 break;
194 }
195 } else {
196 i2c_gd32_handle_tbe(dev);
197 }
198 }
199
i2c_gd32_handle_addsend(const struct device * dev)200 static void i2c_gd32_handle_addsend(const struct device *dev)
201 {
202 struct i2c_gd32_data *data = dev->data;
203 const struct i2c_gd32_config *cfg = dev->config;
204
205 if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len <= 2U)) {
206 I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
207 }
208
209 /* Clear ADDSEND bit */
210 I2C_STAT0(cfg->reg);
211 I2C_STAT1(cfg->reg);
212
213 if (data->is_restart) {
214 data->is_restart = false;
215 data->current->flags &= ~I2C_MSG_RW_MASK;
216 data->current->flags |= I2C_MSG_READ;
217 /* Enter repeated start condition */
218 I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
219
220 return;
221 }
222
223 if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len == 1U)) {
224 /* Enter stop condition */
225 I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
226 }
227 }
228
i2c_gd32_event_isr(const struct device * dev)229 static void i2c_gd32_event_isr(const struct device *dev)
230 {
231 struct i2c_gd32_data *data = dev->data;
232 const struct i2c_gd32_config *cfg = dev->config;
233 uint32_t stat;
234
235 stat = I2C_STAT0(cfg->reg);
236
237 if (stat & I2C_STAT0_SBSEND) {
238 if (data->current->flags & I2C_MSG_READ) {
239 I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 1U;
240 } else {
241 I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 0U;
242 }
243 } else if (stat & I2C_STAT0_ADD10SEND) {
244 I2C_DATA(cfg->reg) = data->addr2;
245 } else if (stat & I2C_STAT0_ADDSEND) {
246 i2c_gd32_handle_addsend(dev);
247 /*
248 * Must handle BTC first.
249 * For I2C_STAT0, BTC is the superset of RBNE and TBE.
250 */
251 } else if (stat & I2C_STAT0_BTC) {
252 i2c_gd32_handle_btc(dev);
253 } else if (stat & I2C_STAT0_RBNE) {
254 i2c_gd32_handle_rbne(dev);
255 } else if (stat & I2C_STAT0_TBE) {
256 i2c_gd32_handle_tbe(dev);
257 }
258 }
259
i2c_gd32_error_isr(const struct device * dev)260 static void i2c_gd32_error_isr(const struct device *dev)
261 {
262 struct i2c_gd32_data *data = dev->data;
263 const struct i2c_gd32_config *cfg = dev->config;
264 uint32_t stat;
265
266 stat = I2C_STAT0(cfg->reg);
267
268 if (stat & I2C_STAT0_BERR) {
269 I2C_STAT0(cfg->reg) &= ~I2C_STAT0_BERR;
270 data->errs |= I2C_GD32_ERR_BERR;
271 }
272
273 if (stat & I2C_STAT0_LOSTARB) {
274 I2C_STAT0(cfg->reg) &= ~I2C_STAT0_LOSTARB;
275 data->errs |= I2C_GD32_ERR_LARB;
276 }
277
278 if (stat & I2C_STAT0_AERR) {
279 I2C_STAT0(cfg->reg) &= ~I2C_STAT0_AERR;
280 data->errs |= I2C_GD32_ERR_AERR;
281 }
282
283 if (data->errs != 0U) {
284 /* Enter stop condition */
285 I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
286
287 k_sem_give(&data->sync_sem);
288 }
289 }
290
i2c_gd32_log_err(struct i2c_gd32_data * data)291 static void i2c_gd32_log_err(struct i2c_gd32_data *data)
292 {
293 if (data->errs & I2C_GD32_ERR_BERR) {
294 LOG_ERR("Bus error");
295 }
296
297 if (data->errs & I2C_GD32_ERR_LARB) {
298 LOG_ERR("Arbitration lost");
299 }
300
301 if (data->errs & I2C_GD32_ERR_AERR) {
302 LOG_ERR("No ACK received");
303 }
304
305 if (data->errs & I2C_GD32_ERR_BUSY) {
306 LOG_ERR("I2C bus busy");
307 }
308 }
309
i2c_gd32_xfer_begin(const struct device * dev)310 static void i2c_gd32_xfer_begin(const struct device *dev)
311 {
312 struct i2c_gd32_data *data = dev->data;
313 const struct i2c_gd32_config *cfg = dev->config;
314
315 k_sem_reset(&data->sync_sem);
316
317 data->errs = 0U;
318 data->is_restart = false;
319
320 /* Default to set ACKEN bit. */
321 I2C_CTL0(cfg->reg) |= I2C_CTL0_ACKEN;
322
323 if (data->current->flags & I2C_MSG_READ) {
324 /* For 2 bytes read, use POAP bit to give NACK for the last data receiving. */
325 if (data->xfer_len == 2U) {
326 I2C_CTL0(cfg->reg) |= I2C_CTL0_POAP;
327 }
328
329 /*
330 * For read on 10 bits address mode, start condition will happen twice.
331 * Transfer sequence as below:
332 * S addr1+W addr2 S addr1+R
333 * Use a is_restart flag to cover this case.
334 */
335 if (data->dev_config & I2C_ADDR_10_BITS) {
336 data->is_restart = true;
337 data->current->flags &= ~I2C_MSG_RW_MASK;
338 }
339 }
340
341 i2c_gd32_enable_interrupts(cfg);
342
343 /* Enter repeated start condition */
344 I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
345 }
346
i2c_gd32_xfer_end(const struct device * dev)347 static int i2c_gd32_xfer_end(const struct device *dev)
348 {
349 struct i2c_gd32_data *data = dev->data;
350 const struct i2c_gd32_config *cfg = dev->config;
351
352 i2c_gd32_disable_interrupts(cfg);
353
354 /* Wait for stop condition is done. */
355 while (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
356 /* NOP */
357 }
358
359 if (data->errs) {
360 return -EIO;
361 }
362
363 return 0;
364 }
365
i2c_gd32_msg_read(const struct device * dev)366 static int i2c_gd32_msg_read(const struct device *dev)
367 {
368 struct i2c_gd32_data *data = dev->data;
369 const struct i2c_gd32_config *cfg = dev->config;
370
371 if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
372 data->errs = I2C_GD32_ERR_BUSY;
373 return -EBUSY;
374 }
375
376 i2c_gd32_xfer_begin(dev);
377
378 k_sem_take(&data->sync_sem, K_FOREVER);
379
380 return i2c_gd32_xfer_end(dev);
381 }
382
i2c_gd32_msg_write(const struct device * dev)383 static int i2c_gd32_msg_write(const struct device *dev)
384 {
385 struct i2c_gd32_data *data = dev->data;
386 const struct i2c_gd32_config *cfg = dev->config;
387
388 if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
389 data->errs = I2C_GD32_ERR_BUSY;
390 return -EBUSY;
391 }
392
393 i2c_gd32_xfer_begin(dev);
394
395 k_sem_take(&data->sync_sem, K_FOREVER);
396
397 return i2c_gd32_xfer_end(dev);
398 }
399
i2c_gd32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)400 static int i2c_gd32_transfer(const struct device *dev,
401 struct i2c_msg *msgs,
402 uint8_t num_msgs,
403 uint16_t addr)
404 {
405 struct i2c_gd32_data *data = dev->data;
406 const struct i2c_gd32_config *cfg = dev->config;
407 struct i2c_msg *current, *next;
408 uint8_t itr;
409 int err = 0;
410
411 current = msgs;
412
413 /* First message flags implicitly contain I2C_MSG_RESTART flag. */
414 current->flags |= I2C_MSG_RESTART;
415
416 for (uint8_t i = 1; i <= num_msgs; i++) {
417
418 if (i < num_msgs) {
419 next = current + 1;
420
421 /*
422 * If there have a R/W transfer state change between messages,
423 * An explicit I2C_MSG_RESTART flag is needed for the second message.
424 */
425 if ((current->flags & I2C_MSG_RW_MASK) !=
426 (next->flags & I2C_MSG_RW_MASK)) {
427 if ((next->flags & I2C_MSG_RESTART) == 0U) {
428 return -EINVAL;
429 }
430 }
431
432 /* Only the last message need I2C_MSG_STOP flag to free the Bus. */
433 if (current->flags & I2C_MSG_STOP) {
434 return -EINVAL;
435 }
436 }
437
438 if ((current->buf == NULL) ||
439 (current->len == 0U)) {
440 return -EINVAL;
441 }
442
443 current++;
444 }
445
446 k_sem_take(&data->bus_mutex, K_FOREVER);
447
448 /* Enable i2c device */
449 I2C_CTL0(cfg->reg) |= I2C_CTL0_I2CEN;
450
451 if (data->dev_config & I2C_ADDR_10_BITS) {
452 data->addr1 = 0xF0 | ((addr & BITS(8, 9)) >> 8U);
453 data->addr2 = addr & BITS(0, 7);
454 } else {
455 data->addr1 = addr & BITS(0, 6);
456 }
457
458 for (uint8_t i = 0; i < num_msgs; i = itr) {
459 data->current = &msgs[i];
460 data->xfer_len = msgs[i].len;
461
462 for (itr = i + 1; itr < num_msgs; itr++) {
463 if ((data->current->flags & I2C_MSG_RW_MASK) !=
464 (msgs[itr].flags & I2C_MSG_RW_MASK)) {
465 break;
466 }
467 data->xfer_len += msgs[itr].len;
468 }
469
470 if (data->current->flags & I2C_MSG_READ) {
471 err = i2c_gd32_msg_read(dev);
472 } else {
473 err = i2c_gd32_msg_write(dev);
474 }
475
476 if (err < 0) {
477 i2c_gd32_log_err(data);
478 break;
479 }
480 }
481
482 /* Disable I2C device */
483 I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
484
485 k_sem_give(&data->bus_mutex);
486
487 return err;
488 }
489
i2c_gd32_configure(const struct device * dev,uint32_t dev_config)490 static int i2c_gd32_configure(const struct device *dev,
491 uint32_t dev_config)
492 {
493 struct i2c_gd32_data *data = dev->data;
494 const struct i2c_gd32_config *cfg = dev->config;
495 uint32_t pclk1, freq, clkc;
496 int err = 0;
497
498 k_sem_take(&data->bus_mutex, K_FOREVER);
499
500 /* Disable I2C device */
501 I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
502
503 (void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
504 (clock_control_subsys_t)&cfg->clkid,
505 &pclk1);
506
507 /* i2c clock frequency, us */
508 freq = pclk1 / 1000000U;
509 if (freq > I2CCLK_MAX) {
510 LOG_ERR("I2C max clock freq %u, current is %u\n",
511 I2CCLK_MAX, freq);
512 err = -ENOTSUP;
513 goto error;
514 }
515
516 /*
517 * Refer from SoC user manual.
518 * In standard mode:
519 * T_high = CLKC * T_pclk1
520 * T_low = CLKC * T_pclk1
521 *
522 * In fast mode and fast mode plus with DTCY=1:
523 * T_high = 9 * CLKC * T_pclk1
524 * T_low = 16 * CLKC * T_pclk1
525 *
526 * T_pclk1 is reciprocal of pclk1:
527 * T_pclk1 = 1 / pclk1
528 *
529 * T_high and T_low construct the bit transfer:
530 * T_high + T_low = 1 / bitrate
531 *
532 * And then, we can get the CLKC equation.
533 * Standard mode:
534 * CLKC = pclk1 / (bitrate * 2)
535 * Fast mode and fast mode plus:
536 * CLKC = pclk1 / (bitrate * 25)
537 *
538 * Variable list:
539 * T_high: high period of the SCL clock
540 * T_low: low period of the SCL clock
541 * T_pclk1: duration of single pclk1 pulse
542 * pclk1: i2c device clock frequency
543 * bitrate: 100 Kbits for standard mode
544 */
545 switch (I2C_SPEED_GET(dev_config)) {
546 case I2C_SPEED_STANDARD:
547 if (freq < I2CCLK_MIN) {
548 LOG_ERR("I2C standard-mode min clock freq %u, current is %u\n",
549 I2CCLK_MIN, freq);
550 err = -ENOTSUP;
551 goto error;
552 }
553 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_I2CCLK;
554 I2C_CTL1(cfg->reg) |= freq;
555
556 /* Standard-mode risetime maximum value: 1000ns */
557 if (freq == I2CCLK_MAX) {
558 I2C_RT(cfg->reg) = I2CCLK_MAX;
559 } else {
560 I2C_RT(cfg->reg) = freq + 1U;
561 }
562
563 /* CLKC = pclk1 / (bitrate * 2) */
564 clkc = pclk1 / (I2C_BITRATE_STANDARD * 2U);
565
566 I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
567 I2C_CKCFG(cfg->reg) |= clkc;
568 /* standard-mode */
569 I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_FAST;
570
571 break;
572 case I2C_SPEED_FAST:
573 if (freq < I2CCLK_FM_MIN) {
574 LOG_ERR("I2C fast-mode min clock freq %u, current is %u\n",
575 I2CCLK_FM_MIN, freq);
576 err = -ENOTSUP;
577 goto error;
578 }
579
580 /* Fast-mode risetime maximum value: 300ns */
581 I2C_RT(cfg->reg) = freq * 300U / 1000U + 1U;
582
583 /* CLKC = pclk1 / (bitrate * 25) */
584 clkc = pclk1 / (I2C_BITRATE_FAST * 25U);
585 if (clkc == 0U) {
586 clkc = 1U;
587 }
588
589 /* Default DCTY to 1 */
590 I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
591 I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
592 I2C_CKCFG(cfg->reg) |= clkc;
593 /* Transfer mode: fast-mode */
594 I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
595
596 #ifdef I2C_FMPCFG
597 /* Disable transfer mode: fast-mode plus */
598 I2C_FMPCFG(cfg->reg) &= ~I2C_FMPCFG_FMPEN;
599 #endif /* I2C_FMPCFG */
600
601 break;
602 #ifdef I2C_FMPCFG
603 case I2C_SPEED_FAST_PLUS:
604 if (freq < I2CCLK_FM_PLUS_MIN) {
605 LOG_ERR("I2C fast-mode plus min clock freq %u, current is %u\n",
606 I2CCLK_FM_PLUS_MIN, freq);
607 err = -ENOTSUP;
608 goto error;
609 }
610
611 /* Fast-mode plus risetime maximum value: 120ns */
612 I2C_RT(cfg->reg) = freq * 120U / 1000U + 1U;
613
614 /* CLKC = pclk1 / (bitrate * 25) */
615 clkc = pclk1 / (I2C_BITRATE_FAST_PLUS * 25U);
616 if (clkc == 0U) {
617 clkc = 1U;
618 }
619
620 /* Default DCTY to 1 */
621 I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
622 I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
623 I2C_CKCFG(cfg->reg) |= clkc;
624 /* Transfer mode: fast-mode */
625 I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
626
627 /* Enable transfer mode: fast-mode plus */
628 I2C_FMPCFG(cfg->reg) |= I2C_FMPCFG_FMPEN;
629
630 break;
631 #endif /* I2C_FMPCFG */
632 default:
633 err = -EINVAL;
634 goto error;
635 }
636
637 data->dev_config = dev_config;
638 error:
639 k_sem_give(&data->bus_mutex);
640
641 return err;
642 }
643
644 static DEVICE_API(i2c, i2c_gd32_driver_api) = {
645 .configure = i2c_gd32_configure,
646 .transfer = i2c_gd32_transfer,
647 #ifdef CONFIG_I2C_RTIO
648 .iodev_submit = i2c_iodev_submit_fallback,
649 #endif
650 };
651
i2c_gd32_init(const struct device * dev)652 static int i2c_gd32_init(const struct device *dev)
653 {
654 struct i2c_gd32_data *data = dev->data;
655 const struct i2c_gd32_config *cfg = dev->config;
656 uint32_t bitrate_cfg;
657 int err;
658
659 err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
660 if (err < 0) {
661 return err;
662 }
663
664 /* Mutex semaphore to protect the i2c api in multi-thread env. */
665 k_sem_init(&data->bus_mutex, 1, 1);
666
667 /* Sync semaphore to sync i2c state between isr and transfer api. */
668 k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
669
670 (void)clock_control_on(GD32_CLOCK_CONTROLLER,
671 (clock_control_subsys_t)&cfg->clkid);
672
673 (void)reset_line_toggle_dt(&cfg->reset);
674
675 cfg->irq_cfg_func();
676
677 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
678
679 i2c_gd32_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
680
681 return 0;
682 }
683
684 #define I2C_GD32_INIT(inst) \
685 PINCTRL_DT_INST_DEFINE(inst); \
686 static void i2c_gd32_irq_cfg_func_##inst(void) \
687 { \
688 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, event, irq), \
689 DT_INST_IRQ_BY_NAME(inst, event, priority), \
690 i2c_gd32_event_isr, \
691 DEVICE_DT_INST_GET(inst), \
692 0); \
693 irq_enable(DT_INST_IRQ_BY_NAME(inst, event, irq)); \
694 \
695 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, error, irq), \
696 DT_INST_IRQ_BY_NAME(inst, error, priority), \
697 i2c_gd32_error_isr, \
698 DEVICE_DT_INST_GET(inst), \
699 0); \
700 irq_enable(DT_INST_IRQ_BY_NAME(inst, error, irq)); \
701 } \
702 static struct i2c_gd32_data i2c_gd32_data_##inst; \
703 const static struct i2c_gd32_config i2c_gd32_cfg_##inst = { \
704 .reg = DT_INST_REG_ADDR(inst), \
705 .bitrate = DT_INST_PROP(inst, clock_frequency), \
706 .clkid = DT_INST_CLOCKS_CELL(inst, id), \
707 .reset = RESET_DT_SPEC_INST_GET(inst), \
708 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
709 .irq_cfg_func = i2c_gd32_irq_cfg_func_##inst, \
710 }; \
711 I2C_DEVICE_DT_INST_DEFINE(inst, \
712 i2c_gd32_init, NULL, \
713 &i2c_gd32_data_##inst, &i2c_gd32_cfg_##inst, \
714 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
715 &i2c_gd32_driver_api); \
716
717 DT_INST_FOREACH_STATUS_OKAY(I2C_GD32_INIT)
718
