1/* 2 * Copyright (c) 2023 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include "gpio_common.dtsi" 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu: cpu@0 { 20 device_type = "cpu"; 21 compatible = "intel,alder-lake", "intel,x86_64"; 22 d-cache-line-size = <64>; 23 reg = <0>; 24 }; 25 26 cpu@1 { 27 device_type = "cpu"; 28 compatible = "intel,alder-lake"; 29 d-cache-line-size = <64>; 30 reg = <1>; 31 }; 32 33 }; 34 35 dram0: memory@0 { 36 device_type = "memory"; 37 reg = <0x0 DT_DRAM_SIZE>; 38 }; 39 40 intc: ioapic@fec00000 { 41 compatible = "intel,ioapic"; 42 #address-cells = <1>; 43 #interrupt-cells = <3>; 44 reg = <0xfec00000 0x1000>; 45 interrupt-controller; 46 }; 47 48 intc_loapic: loapic@fee00000 { 49 compatible = "intel,loapic"; 50 reg = <0xfee00000 0x1000>; 51 interrupt-controller; 52 #interrupt-cells = <3>; 53 #address-cells = <1>; 54 }; 55 56 acpi { 57 gpio_a: gpio_a { 58 acpi-hid = "INTC1057"; 59 acpi-uid = "2"; 60 group-index = <0x02>; 61 status = "okay"; 62 }; 63 64 gpio_b: gpio_b { 65 acpi-hid = "INTC1057"; 66 acpi-uid = "0"; 67 group-index = <0x0>; 68 status = "okay"; 69 }; 70 71 gpio_c: gpio_c { 72 acpi-hid = "INTC1057"; 73 acpi-uid = "0"; 74 group-index = <0x0B>; 75 status = "okay"; 76 }; 77 78 gpio_d: gpio_d { 79 acpi-hid = "INTC1057"; 80 acpi-uid = "0"; 81 group-index = <0x8>; 82 status = "okay"; 83 }; 84 85 gpio_e: gpio_e { 86 acpi-hid = "INTC1057"; 87 acpi-uid = "0"; 88 group-index = <0xE>; 89 status = "okay"; 90 }; 91 92 gpio_f: gpio_f { 93 acpi-hid = "INTC1057"; 94 acpi-uid = "0"; 95 group-index = <0xC>; 96 status = "okay"; 97 }; 98 99 gpio_h: gpio_h { 100 acpi-hid = "INTC1057"; 101 acpi-uid = "0"; 102 group-index = <0x7>; 103 status = "okay"; 104 }; 105 106 gpio_i: gpio_i { 107 acpi-hid = "INTC1057"; 108 acpi-uid = "0"; 109 group-index = <0x9>; 110 status = "okay"; 111 }; 112 113 gpio_s: gpio_s { 114 acpi-hid = "INTC1057"; 115 acpi-uid = "0"; 116 group-index = <0x6>; 117 status = "okay"; 118 }; 119 120 gpio_r: gpio_r { 121 acpi-hid = "INTC1057"; 122 acpi-uid = "0"; 123 group-index = <0x3>; 124 status = "okay"; 125 }; 126 127 gpio_t: gpio_t { 128 acpi-hid = "INTC1057"; 129 acpi-uid = "0"; 130 group-index = <0x1>; 131 status = "okay"; 132 }; 133 134 gpio_v: gpio_v { 135 acpi-hid = "INTC1057"; 136 acpi-uid = "0"; 137 group-index = <0xA>; 138 status = "okay"; 139 }; 140 }; 141 142 pcie0: pcie0 { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 compatible = "pcie-controller"; 146 acpi-hid = "PNP0A08"; 147 ranges; 148 149 smbus0: smbus0 { 150 compatible = "intel,pch-smbus"; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 vendor-id = <0x8086>; 154 device-id = <0x54a3>; 155 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 156 interrupt-parent = <&intc>; 157 158 status = "okay"; 159 }; 160 161 uart0: uart0 { 162 compatible = "ns16550"; 163 164 vendor-id = <0x8086>; 165 device-id = <0x54a8>; 166 167 clock-frequency = <1843200>; 168 current-speed = <115200>; 169 reg-shift = <2>; 170 171 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 172 interrupt-parent = <&intc>; 173 status = "disabled"; 174 }; 175 176 uart1_dma: uart1_dma { 177 compatible = "intel,lpss"; 178 #dma-cells = <1>; 179 status = "disabled"; 180 }; 181 182 uart1: uart1 { 183 compatible = "ns16550"; 184 vendor-id = <0x8086>; 185 device-id = <0x54A9>; 186 clock-frequency = <1843200>; 187 current-speed = <115200>; 188 reg-shift = <2>; 189 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 190 interrupt-parent = <&intc>; 191 dmas = <&uart1_dma 0>, <&uart1_dma 1>; 192 dma-names = "tx", "rx"; 193 status = "disabled"; 194 }; 195 196 uart2_dma: uart2_dma { 197 compatible = "intel,lpss"; 198 #dma-cells = <1>; 199 status = "disabled"; 200 }; 201 202 uart2: uart2 { 203 compatible = "ns16550"; 204 vendor-id = <0x8086>; 205 device-id = <0x54C7>; 206 clock-frequency = <1843200>; 207 current-speed = <115200>; 208 reg-shift = <2>; 209 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 210 interrupt-parent = <&intc>; 211 dmas = <&uart2_dma 0>, <&uart2_dma 1>; 212 dma-names = "tx", "rx"; 213 214 status = "disabled"; 215 }; 216 217 i2c0: i2c0 { 218 compatible = "snps,designware-i2c"; 219 clock-frequency = <I2C_BITRATE_STANDARD>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 vendor-id = <0x8086>; 223 device-id = <0x54e8>; 224 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 225 interrupt-parent = <&intc>; 226 227 status = "okay"; 228 }; 229 230 i2c1: i2c1 { 231 compatible = "snps,designware-i2c"; 232 clock-frequency = <I2C_BITRATE_STANDARD>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 vendor-id = <0x8086>; 236 device-id = <0x54e9>; 237 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 238 interrupt-parent = <&intc>; 239 240 status = "disabled"; 241 }; 242 243 i2c2: i2c2 { 244 compatible = "snps,designware-i2c"; 245 clock-frequency = <I2C_BITRATE_STANDARD>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 vendor-id = <0x8086>; 249 device-id = <0x54ea>; 250 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 251 interrupt-parent = <&intc>; 252 253 status = "disabled"; 254 }; 255 256 i2c3: i2c3 { 257 compatible = "snps,designware-i2c"; 258 clock-frequency = <I2C_BITRATE_STANDARD>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 vendor-id = <0x8086>; 262 device-id = <0x54eb>; 263 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 264 interrupt-parent = <&intc>; 265 266 status = "disabled"; 267 }; 268 269 i2c4: i2c4 { 270 compatible = "snps,designware-i2c"; 271 clock-frequency = <I2C_BITRATE_STANDARD>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 vendor-id = <0x8086>; 275 device-id = <0x54c5>; 276 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 277 interrupt-parent = <&intc>; 278 279 status = "disabled"; 280 }; 281 282 i2c5: i2c5 { 283 compatible = "snps,designware-i2c"; 284 clock-frequency = <I2C_BITRATE_STANDARD>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 vendor-id = <0x8086>; 288 device-id = <0x54c6>; 289 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 290 interrupt-parent = <&intc>; 291 292 status = "disabled"; 293 }; 294 295 spi0: spi0 { 296 compatible = "intel,penwell-spi"; 297 vendor-id = <0x8086>; 298 device-id = <0x54aa>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 pw,cs-mode = <0>; 302 pw,cs-output = <0>; 303 pw,fifo-depth = <64>; 304 cs-gpios = <&gpio_e 10 GPIO_ACTIVE_LOW>; 305 clock-frequency = <100000000>; 306 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 307 interrupt-parent = <&intc>; 308 status = "okay"; 309 }; 310 311 spi1: spi1 { 312 compatible = "intel,penwell-spi"; 313 vendor-id = <0x8086>; 314 device-id = <0x54ab>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 pw,cs-mode = <0>; 318 pw,cs-output = <0>; 319 pw,fifo-depth = <64>; 320 cs-gpios = <&gpio_f 16 GPIO_ACTIVE_LOW>; 321 clock-frequency = <100000000>; 322 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 323 interrupt-parent = <&intc>; 324 status = "disabled"; 325 }; 326 327 spi2: spi2 { 328 compatible = "intel,penwell-spi"; 329 vendor-id = <0x8086>; 330 device-id = <0x54fb>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 pw,cs-mode = <0>; 334 pw,cs-output = <0>; 335 pw,fifo-depth = <64>; 336 cs-gpios = <&gpio_d 9 GPIO_ACTIVE_LOW>; 337 clock-frequency = <100000000>; 338 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 339 interrupt-parent = <&intc>; 340 status = "disabled"; 341 }; 342 343 emmc: emmc0 { 344 compatible = "intel,emmc-host"; 345 vendor-id = <0x8086>; 346 device-id = <0x54C4>; 347 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 348 interrupt-parent = <&intc>; 349 350 max-bus-freq = <200000000>; 351 min-bus-freq = <400000>; 352 power-delay-ms = <500>; 353 mmc-hs400-1_8v; 354 mmc-hs200-1_8v; 355 356 mmc { 357 compatible = "zephyr,mmc-disk"; 358 disk-name = "SD2"; 359 bus-width = <8>; 360 status = "okay"; 361 }; 362 363 status = "okay"; 364 }; 365 }; 366 367 soc { 368 #address-cells = <1>; 369 #size-cells = <1>; 370 compatible = "simple-bus"; 371 ranges; 372 373 vtd: vtd@fed91000 { 374 compatible = "intel,vt-d"; 375 reg = <0xfed91000 0x1000>; 376 status = "okay"; 377 }; 378 379 uart0_legacy: uart@3f8 { 380 compatible = "ns16550"; 381 reg = <0x000003f8 0x100>; 382 io-mapped; 383 clock-frequency = <1843200>; 384 interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 385 interrupt-parent = <&intc>; 386 reg-shift = <0>; 387 status = "okay"; 388 }; 389 390 tgpio: tgpio@fe001200 { 391 compatible = "intel,timeaware-gpio"; 392 reg = <0xfe001200 0x100>; 393 timer-clock = <19200000>; 394 max-pins = <2>; 395 status = "okay"; 396 }; 397 398 hpet: hpet@fed00000 { 399 compatible = "intel,hpet"; 400 reg = <0xfed00000 0x400>; 401 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 402 interrupt-parent = <&intc>; 403 404 status = "okay"; 405 }; 406 407 rtc: counter: rtc@70 { 408 compatible = "motorola,mc146818"; 409 reg = <0x70 0x0D 0x71 0x0D>; 410 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 411 interrupt-parent = <&intc>; 412 alarms-count = <1>; 413 414 status = "okay"; 415 }; 416 417 tco_wdt: tco_wdt@400 { 418 compatible = "intel,tco-wdt"; 419 reg = <0x0400 0x20>; 420 status = "disabled"; 421 }; 422 423 pwm0: pwm0@fd6d0000 { 424 compatible = "intel,blinky-pwm"; 425 reg = <0xfd6d0000 0x400>; 426 reg-offset = <0x204>; 427 clock-frequency = <32768>; 428 max-pins = <1>; 429 #pwm-cells = <2>; 430 status = "okay"; 431 }; 432 }; 433}; 434
