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/Zephyr-latest/dts/bindings/counter/
Dnordic,nrf-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-timer"
14 cc-num:
19 max-bit-width:
22 description: Maximum bit width supported
27 max-frequency:
40 description: Prescaler value determines frequency (max-frequency/2^prescaler)
/Zephyr-latest/dts/common/nordic/
Dnrf9280.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
10 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
11 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
12 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
13 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
15 /delete-node/ &sw_pwm;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
[all …]
Dnrf54l_05_10_15.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
12 /delete-node/ &sw_pwm;
19 #address-cells = <1>;
20 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "arm,cortex-m33f";
30 clock-frequency = <DT_FREQ_M(128)>;
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Dnrf54l20.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
12 /delete-node/ &sw_pwm;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,cortex-m33f";
26 clock-frequency = <DT_FREQ_M(128)>;
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Dnrf54h20.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
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/Zephyr-latest/dts/arm/nordic/
Dnrf52832.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4f";
23 #address-cells = <1>;
[all …]
Dnrf52820.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/regulator/nrf5x.h>
14 zephyr,bt-hci = &bt_hci_controller;
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4";
27 #address-cells = <1>;
28 #size-cells = <1>;
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Dnrf51822.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv6-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-adc.h>
9 zephyr,bt-hci = &bt_hci_controller;
11 zephyr,flash-controller = &flash_controller;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0";
27 compatible = "nordic,nrf-ficr";
29 #nordic,ficr-cells = <1>;
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Dnrf52840.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4f";
23 #address-cells = <1>;
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Dnrf52833.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
14 zephyr,bt-hci = &bt_hci_controller;
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4f";
27 #address-cells = <1>;
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Dnrf91_peripherals.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 flash_controller: flash-controller@39000 {
8 compatible = "nordic,nrf91-flash-controller";
10 partial-erase;
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "soc-nv-flash";
18 erase-block-size = <4096>;
19 write-block-size = <4>;
24 compatible = "nordic,nrf-saadc";
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Dnrf5340_cpunet.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
12 zephyr,bt-hci = &bt_hci_controller;
14 zephyr,flash-controller = &flash_controller;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-m33";
25 #address-cells = <1>;
26 #size-cells = <1>;
29 compatible = "arm,armv8m-mpu";
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Dnrf52805.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
14 zephyr,bt-hci = &bt_hci_controller;
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4";
32 compatible = "nordic,nrf-ficr";
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Dnrf52810.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
6 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 zephyr,bt-hci = &bt_hci_controller;
12 zephyr,flash-controller = &flash_controller;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
23 #address-cells = <1>;
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Dnrf52811.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/nrf-saadc-v2.h>
10 #include <zephyr/dt-bindings/regulator/nrf5x.h>
14 zephyr,bt-hci = &bt_hci_controller;
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4";
27 #address-cells = <1>;
[all …]
Dnrf5340_cpuapp_peripherals.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/regulator/nrf5x.h>
10 compatible = "nordic,nrf-dcnf";
15 oscillators: clock-controller@4000 {
16 compatible = "nordic,nrf53-oscillators";
20 compatible = "nordic,nrf53-lfxo";
21 #clock-cells = <0>;
22 clock-frequency = <32768>;
26 compatible = "nordic,nrf53-hfxo";
27 #clock-cells = <0>;
[all …]
/Zephyr-latest/drivers/dma/
Ddma_pl330.h4 * SPDX-License-Identifier: Apache-2.0
14 * Max burst length and max burst size for 32bit system with
15 * 128bit bus width for memory to memory data transfer
40 * PL330 has 32bit registers for source and destination addresses
44 /* PL330 supports max 16MB dma based on AXI bus size */
Ddma_dw_axi.c4 * SPDX-License-Identifier: Apache-2.0
17 #define DEV_CFG(_dev) ((const struct dma_dw_axi_dev_cfg *)(_dev)->config)
18 #define DEV_DATA(_dev) ((struct dma_dw_axi_dev_data *const)(_dev)->data)
26 * when blen is 1 then set msize to zero otherwise find most significant bit set
29 #define DMA_DW_AXI_GET_MSIZE(blen) ((blen == 1) ? (0U) : (find_msb_set(blen) - 2U))
53 /* channel resume bit pos */
91 /* bitfield configuration for multi-block transfer */
113 /* source status enable bit */
115 /* destination status enable bit */
119 /* source burst length(considered when corresponding enable bit is set) */
[all …]
Ddma_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
45 DMA->DMA_REQ_MUX_REG = \
46 (DMA->DMA_REQ_MUX_REG & ~(0xf << DMA_MUX_SHIFT((_idx)))) | \
50 ((DMA->DMA_REQ_MUX_REG >> DMA_MUX_SHIFT((_idx))) & 0xf)
93 * DMA bus width indicating how many bytes are retrived/written per transfer.
94 * Note that the bus width is the same for the source and destination.
173 if (DMA_CTRL_REG_GET_FIELD(DMA_ON, regs->DMA_CTRL_REG)) { in dma_smartbond_is_dma_active()
207 DMA->DMA_CLEAR_INT_REG |= BIT(channel); in dma_smartbond_set_channel_status()
209 DMA->DMA_INT_MASK_REG |= BIT(channel); in dma_smartbond_set_channel_status()
218 DMA_CTRL_REG_SET_FIELD(DMA_ON, regs->DMA_CTRL_REG, 0x1); in dma_smartbond_set_channel_status()
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/Zephyr-latest/boards/weact/mini_stm32h7b0/
Dmini_stm32h7b0.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/h7/stm32h7b0vbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
15 compatible = "weact,mini-stm32h7b0";
19 zephyr,shell-uart = &usb_cdc_acm_uart;
26 compatible = "gpio-leds";
34 compatible = "gpio-keys";
43 compatible = "zephyr,mipi-dbi-spi";
[all …]
/Zephyr-latest/drivers/flash/
Dflash_ifx_cat1_qspi.c5 * SPDX-License-Identifier: Apache-2.0
67 /* The 8-bit command. 1 x I/O read command. */
69 /* The width of the command transfer. */
71 /* The width of the address transfer. */
73 /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
75 /* The width of the mode command transfer. */
79 /* The width of the data transfer. */
92 * https://iot-webserver.aus.cypress.com/projects/iot_release/
93 * ASSETS/repo/mtb-pdl-cat1/develop/Latest/deploy/docs/
127 /* Specifies the command to read the QE-containing status register. */
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/Zephyr-latest/include/zephyr/drivers/
Dsdhc.h4 * SPDX-License-Identifier: Apache-2.0
37 #define SDHC_TIMEOUT_FOREVER (-1)
51 unsigned int retries; /*!< Max number of retries */
98 * @brief SD host controller bus width
100 * Only relevant in SD mode, SPI does not support bus width. UHS cards will
101 * use 4 bit data bus, all cards start in 1 bit mode
113 * to the bus. Cards start with legacy timing, but UHS-II cards can go up to
168 unsigned int max_blk_len: 2; /**< Max block length */
169 unsigned int bus_8_bit_support: 1; /**< 8-bit Support for embedded device */
170 unsigned int bus_4_bit_support: 1; /**< 4 bit bus support */
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/Zephyr-latest/dts/bindings/display/
Dgalaxycore,gc9x01x.yaml2 # Copyright (c) 2023 Amrith Venkat Kesavamoorthi <amrith@mr-beam.org>
4 # SPDX-License-Identifier: Apache-2.0
12 - GC9101A: (Waveshare 240x240, 1.28inch round lcd display 240x240)
18 compatible = "zephyr,mipi-dbi-spi";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 spi-dev = <&spi2>;
23 dc-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
29 mipi-max-frequency = <DT_FREQ_M(100)>;
[all …]
/Zephyr-latest/drivers/sdhc/
Dintel_emmc_host.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Bit map for command Register */
18 /* Bit map for Transfer Mode Register */
31 /* Bit map for Block Size and GAP Register */
43 #define EMMC_HOST_ADMA_INTR_EN BIT(2)
44 #define EMMC_HOST_ADMA_BUFF_LAST BIT(1)
45 #define EMMC_HOST_ADMA_BUFF_VALID BIT(0)
47 /* Bit Map and length details for Clock Control Register */
54 /* Bit Map for Host Control 1 Register */
64 #define EMMC_HOST_SW_RESET_REG_ALL BIT(0)
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/Zephyr-latest/drivers/watchdog/
Dwdt_xilinx_axi.c10 * SPDX-License-Identifier: Apache-2.0
30 CSR0_WRS = BIT(3),
31 CSR0_WDS = BIT(2),
32 CSR0_EWDT1 = BIT(1),
33 CSR0_EWDT2 = BIT(0),
37 CSR1_EWDT2 = BIT(0),
63 const struct xilinx_wdt_axi_config *config = dev->config; in wdt_xilinx_axi_setup()
64 struct xilinx_wdt_axi_data *data = dev->data; in wdt_xilinx_axi_setup()
65 k_spinlock_key_t key = k_spin_lock(&data->lock); in wdt_xilinx_axi_setup()
68 if (!data->timeout_active) { in wdt_xilinx_axi_setup()
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