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/Zephyr-latest/dts/bindings/can/
Dst,stm32-bxcan.yaml1 description: STM32 CAN controller
3 compatible: "st,stm32-bxcan"
5 include: [can-controller.yaml, pinctrl-device.yaml]
8 reg:
17 pinctrl-0:
20 pinctrl-names:
23 master-can-reg:
25 description: master can reg when different from current instance
/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
7 have internal counter that either can be used independently or used
8 as a reference timebase (master bus) for other channels.
10 compatible: "nxp,s32-emios"
15 reg:
21 interrupt-names:
27 clock-divider:
33 internal-cnt:
39 child-binding:
40 child-binding:
[all …]
/Zephyr-latest/dts/bindings/spi/
Dnordic,nrf-spi-common.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-controller.yaml, pinctrl-device.yaml, nordic-clockpin.yaml]
9 reg:
15 pinctrl-0:
18 pinctrl-names:
21 max-frequency:
25 Maximum data rate the SPI peripheral can be driven at, in Hz. This
28 overrun-character:
34 easydma-maxcnt-bits:
41 wake-gpios:
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Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: spi
11 reg:
13 spi-max-frequency:
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
37 list (see dt-bindings/spi/spi.h)
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/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8m.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "cdns,tensilica-xtensa-lx6";
19 reg = <0>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clic: interrupt-controller@0 {
25 compatible = "cdns,xtensa-core-intc";
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f446.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
14 compatible = "st,stm32f411-plli2s-clock";
19 compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
22 compatible = "st,stm32-i2s";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 reg = <0x40013000 0x400>;
30 dma-names = "tx", "rx";
[all …]
Dstm32f412.dtsi2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f411-plli2s-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32-clock-mux";
29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
31 pinctrl: pin-controller@40020000 {
[all …]
Dstm32f405.dtsi5 * SPDX-License-Identifier: Apache-2.0
16 compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
18 pinctrl: pin-controller@40020000 {
19 reg = <0x40020000 0x2400>;
22 compatible = "st,stm32-gpio";
23 gpio-controller;
24 #gpio-cells = <2>;
25 reg = <0x40021400 0x400>;
30 compatible = "st,stm32-gpio";
31 gpio-controller;
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/Zephyr-latest/dts/arm/st/l4/
Dstm32l496.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 clk_hsi48: clk-hsi48 {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <DT_FREQ_M(48)>;
21 compatible = "st,stm32l496", "st,stm32l4", "simple-bus";
29 compatible = "st,stm32-i2c-v2";
30 clock-frequency = <I2C_BITRATE_STANDARD>;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/i2c/
Datmel,sam-i2c-twim.yaml1 # Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
10 always a bus master and can transfer sequential or single bytes. Multiple
11 master capability is supported. Arbitration of the bus is performed
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
22 std-data-slew-lim = <0>;
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/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
[all …]
/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
13 reg:
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
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/Zephyr-latest/dts/arm/st/f1/
Dstm32f105.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
12 /delete-node/ pll;
15 #clock-cells = <0>;
16 compatible = "st,stm32f105-pll-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32f105-pll2-clock";
29 compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
31 flash-controller@40022000 {
33 erase-block-size = <DT_SIZE_K(2)>;
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dst,stm32f1-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
17 reg:
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
[all …]
Dst,stm32-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
17 reg:
20 remap-pa11:
25 remap-pa12:
30 remap-pa11-pa12:
35 child-binding:
[all …]
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst6 STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz
7 wireless module. It supports Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0,
10 module on other boards as HCI layer (Specefically B-U585I-IOT02A Development board).
14 - Bluetooth module in SiP-LGA86 package
15 - Integrated chip antenna
16 - Bluetooth|reg| Low Energy 5.4, Zigbee|reg| 3.0, OpenThread certified
18 - IEEE 802.15.4-2011 MAC PHY Supports 2 Mbits/s
19 - Frequency band 2402-2480 MHz
20 - Advertising extension
21 - Tx output power up to +6 dBm
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The SMC allows to interface with static-memory mapped external devices such as
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
13 The SMC controller can have up to 4 children defining the connected external
14 memory devices. The reg property is set to the device's Chip Select.
19 pinctrl-0 = <&smc_default>;
20 pinctrl-names = "default";
23 reg = <0>;
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_sifive.c4 * SPDX-License-Identifier: Apache-2.0
18 #include "i2c-priv.h"
22 #define I2C_REG(config, reg) ((mem_addr_t) ((config)->base + reg)) argument
23 #define IS_SET(config, reg, value) (sys_read8(I2C_REG(config, reg)) & (value)) argument
73 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_busy()
82 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_send_addr()
103 return -EIO; in i2c_sifive_send_addr()
113 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_write_msg()
123 for (uint32_t i = 0; i < msg->len; i++) { in i2c_sifive_write_msg()
128 /* Put data in transmit reg */ in i2c_sifive_write_msg()
[all …]
Di2c_dw.c1 /* dw_i2c.c - I2C file for Design Ware */
5 * Copyright (c) 2022 Andrei-Edward Popa
7 * SPDX-License-Identifier: Apache-2.0
49 #include "i2c-priv.h"
59 uint32_t reg; in i2c_dw_enable_idma() local
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
66 reg = read_dma_cr(reg_base); in i2c_dw_enable_idma()
67 reg &= ~DW_IC_DMA_ENABLE; in i2c_dw_enable_idma()
68 write_dma_cr(reg, reg_base); in i2c_dw_enable_idma()
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
[all …]
Di2c_cc32xx.c4 * SPDX-License-Identifier: Apache-2.0
29 #include "i2c-priv.h"
44 (((const struct i2c_cc32xx_config *const)(dev)->config)->base)
48 * are no interrupts received which can distinguish between read and write
53 * I2C API without having to re-read I2C registers.
91 return -EINVAL; in i2c_cc32xx_configure()
95 return -EINVAL; in i2c_cc32xx_configure()
106 return -EINVAL; in i2c_cc32xx_configure()
118 struct i2c_cc32xx_data *data = dev->data; in i2c_cc32xx_prime_transfer()
122 data->msg = *msg; in i2c_cc32xx_prime_transfer()
[all …]
/Zephyr-latest/boards/st/sensortile_box_pro/doc/
Dindex.rst6 The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU
7 and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using
10 The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable
14 More information about the board can be found at the `SensorTile.box PRO website`_.
23 - Pedometer optimized for belt positioning
24 - Baby crying detection with Cloud AI learning
25 - Barometer / environmental monitoring
26 - Vehicle / goods tracking
27 - Vibration monitoring
28 - Compass and inclinometer
[all …]
/Zephyr-latest/boards/st/nucleo_l432kc/doc/
Dindex.rst6 The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU
10 - STM32 microcontroller in UFQFPN32 package
11 - Arduino Uno V3 connectivity
12 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector
13 - Flexible board power supply:
15 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
16 - Power management access point
18 - Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3)
19 - One push-button: RESET
21 More information about the board can be found at the `Nucleo L432KC website`_.
[all …]
/Zephyr-latest/boards/96boards/argonkey/doc/
Dindex.rst13 family products. It can also be used as a standalone board.
26 - STM32F412CG in UFQFPN48 package
27 - ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
28 - 100 MHz max CPU frequency
29 - 1.8V work voltage
30 - 1024 KB Flash
31 - 256 KB SRAM
32 - On board sensors:
34 - Humidity: STMicro HTS221
35 - Temperature/Pressure: STMicro LPS22HB
[all …]
/Zephyr-latest/boards/weact/stm32f405_core/doc/
Dindex.rst6 The WeAct STM32F405 Core Board is an extremely low cost and bare-bones
8 This is the 64-pin variant of the STM32F405x series,
18 - STM32F405RG in QFPN64 package
19 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time
20 accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory
21 - 168 MHz max CPU frequency
22 - VDD from 1.7 V to 3.6 V
23 - 1 MB Flash
24 - 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory)
25 - GPIO with external interrupt capability
[all …]
/Zephyr-latest/boards/st/nucleo_wb55rg/doc/
Dnucleo_wb55rg.rst6 The Nucleo WB55RG board is a multi-protocol wireless and ultra-low-power device
7 embedding a powerful and ultra-low-power radio compliant with the Bluetooth®
8 Low Energy (BLE) SIG specification v5.0 and with IEEE 802.15.4-2011.
11 - STM32 microcontroller in VFQFPN68 package
12 - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.0 and
13 IEEE 802.15.4-2011 PHY and MAC
14 - Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
15 - Three user LEDs
16 - Board connector: USB user with Micro-B
17 - Two types of extension resources:
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