1# Copyright (c) 2018 Nordic Semiconductor ASA
2# SPDX-License-Identifier: Apache-2.0
3
4# Common fields for Nordic nRF family SPI peripherals
5
6include: [spi-controller.yaml, pinctrl-device.yaml, nordic-clockpin.yaml]
7
8properties:
9  reg:
10    required: true
11
12  interrupts:
13    required: true
14
15  pinctrl-0:
16    required: true
17
18  pinctrl-names:
19    required: true
20
21  max-frequency:
22    type: int
23    required: true
24    description: |
25      Maximum data rate the SPI peripheral can be driven at, in Hz. This
26      property must be set at SoC level DTS files.
27
28  overrun-character:
29    default: 0xff
30    description: |
31      Configurable, defaults to 0xff (line high), the most common value used
32      in SPI transfers.
33
34  easydma-maxcnt-bits:
35    type: int
36    required: true
37    description: |
38      Maximum number of bits available in the EasyDMA MAXCNT register. This
39      property must be set at SoC level DTS files.
40
41  wake-gpios:
42    type: phandle-array
43    description: |
44      Optional bi-directional line that allows SPI master to indicate to SPI
45      slave (by setting the line high) that a transfer is to occur, so that
46      the latter can prepare (and indicate its readiness) for handling that
47      transfer when it is actually needed, and stay in any desired low-power
48      state otherwise.
49      The protocol is as follows:
50      - initially, SPI slave configures its WAKE line pin as an input and SPI
51        master keeps the line in the low state
52      - when a transfer is to be performed, SPI master configures its WAKE
53        line pin as an input with pull-up; this changes the line state to
54        high but allows SPI slave to override that state
55      - when SPI slave detects the high state of the WAKE line, it prepares
56        for the transfer and when everything is ready, it drives the WAKE
57        line low by configuring its pin as an output
58      - the generated high-to-low transition on the WAKE line is a signal
59        to SPI master that it can proceed with the transfer
60      - SPI slave releases the line by configuring its pin back to be an input
61        and SPI master again keeps the line in the low state
62      Please note that the line must be configured and properly handled on
63      both sides for the mechanism to work correctly.
64