1# Copyright(c) 2024 Intel Corporation.
2# SPDX - License - Identifier : Apache - 2.0
3
4compatible: "snps,dwcxgmac"
5
6description: Synopsys DesignWareCore XGMAC
7
8include:
9  - name: reset-device.yaml
10  - name: ethernet-controller.yaml
11
12properties:
13  reg:
14    required: true
15  interrupts:
16    required: true
17  max-frame-size:
18    type: int
19    default: 1518
20    description: |
21      Maximum ethernet frame size.  The current ethernet frame sizes
22      supported by hardware are standard and jumbo (up to 16KB) frames. This
23      means that normally xgmac will reject any frame above max-frame-size
24      value.  The default value is 1518, which represents an usual
25      IEEE 802.3 ethernet frame:
26        Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes
27  max-speed:
28    type: int
29    enum:
30      - 10
31      - 100
32      - 1000
33      - 2500
34    default: 1000
35    description: |
36      This specifies maximum speed in Mbit/s supported by the device.  The
37      xgmac driver supports 10Mbit/s, 100Mbit/s, 1000Mbit/s, and 2500Mbit/s.  Using 1000,
38      as default value, enables driver to configure 10 and 100Mbit/s speeds.
39      2500Mbit/s speed can be used only with Soft PCS. When selected driver assumes
40      soft PCS is connected to XGMAC through GMII. make sure the phy-connection-type is
41      selected as gmii when 2500Mbit/s speed is selected.
42  tx-fifo-size:
43    type: int
44    enum:
45      - 1024
46      - 2048
47      - 4096
48      - 8192
49      - 16384
50      - 32768
51      - 65536
52      - 131072
53      - 262144
54    default: 32768
55    description: |
56      Specifies the size of the MTL Transmit FIFO
57  rx-fifo-size:
58    type: int
59    enum:
60      - 1024
61      - 2048
62      - 4096
63      - 8192
64      - 16384
65      - 32768
66      - 65536
67      - 131072
68      - 262144
69    default: 32768
70    description: |
71      Specifies the size of the MTL Receive FIFO
72  num-dma-ch:
73    type: int
74    required: true
75    description: |
76      Number of dma channels range: 1 to 8.
77  num-tx-queues:
78    type: int
79    required: true
80    description: |
81      Number of hardware TX queues range: 1 to 8.
82  num-rx-queues:
83    type: int
84    required: true
85    description: |
86      Number of hardware RX queues range: 1 to 8.
87  num-tc:
88    type: int
89    default: 1
90    description: |
91      Number of traffic classes range: 1 to 7.
92  full-duplex-mode-en:
93    type: boolean
94    required: true
95    description: |
96      MAC communication mode to full duplex mode.
97  wr-osr-lmt:
98    type: int
99    default: 31
100    description: |
101      AXI Maximum Write Outstanding Request Limit.This value
102      limits the maximum outstanding request on the AXI write
103      interface. Maximum outstanding requests = WR_OSR_LMT + 1
104  rd-osr-lmt:
105    type: int
106    default: 31
107    description: |
108      AXI Maximum Read Outstanding Request Limit.This value
109      limits the maximum outstanding request on the AXI read
110      interface. Maximum outstanding requests = WR_OSR_LMT + 1
111  pbl:
112    type: int
113    default: 32
114    description: |
115      Programmable burst length range: 4,5,16,32,64,128,256
116  edma-tdps:
117    type: int
118    default: 1
119    description: |
120      Tx Descriptor Pre-fetch threshold Size.
121      This field controls the threshold in the Descriptor cache after
122      which the DMA starts pre-fetching the TxDMA descriptors. The
123      DMA engine for all TxDMA channels initiate requests for the
124      descriptor fetches as soon as the number of descriptors in the
125      cache memory for that DMA channel, falls below or equal to
126      the programmed threshold (each descriptor is 16 bytes)
127      Range: 0,1,2,3,4,5
128  edma-rdps:
129    type: int
130    default: 1
131    description: |
132      Rx Descriptor Pre-fetch threshold Size.
133      This field controls the threshold in the Descriptor cache after
134      which the DMA starts pre-fetching the RxDMA descriptors. The
135      DMA engine for all RxDMA channels initiate requests for the
136      descriptor fetches as soon as the number of descriptors in the
137      cache memory for that DMA channel, falls below or equal to
138      the programmed threshold (each descriptor is 16 bytes)
139      Range: 0,1,2,3,4,5
140  pblx8:
141    type: boolean
142    description: |
143      8xPBL mode.
144      When this is set to true, the PBL value is multiplied eight times.
145      Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256
146      beats depending on the PBL value.
147  ubl:
148    type: boolean
149    description: |
150      AXI Undefined Burst Length.
151      1: The AXI master can perform burst transfers that are equal to or less
152      than the maximum allowed burst length enabled.
153      0: The AXI master performs one of the following burst transfers: Burst
154      transfers of fixed burst lengths as indicated by the BLEN256, BLEN128,
155      BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field.
156  blen4:
157    type: boolean
158    description: |
159      AXI Burst Length 4.
160      When this enabled and the mixed_burst is disabled, the AXI master
161      can select a burst length of 4 on the AXI interface.
162      When the mixed_burst enabled, enabling this field has no effect.
163  blen8:
164    type: boolean
165    description: |
166      AXI Burst Length 8.
167      When this enabled and the mixed_burst is disabled, the AXI master
168      can select a burst length of 8 on the AXI interface.
169      When the mixed_burst enabled, enabling this field has no effect.
170  blen16:
171    type: boolean
172    description: |
173      AXI Burst Length 16.
174      When this enabled and the mixed_burst is disabled, the AXI master
175      can select a burst length of 16 on the AXI interface.
176      When the mixed_burst enabled, enabling this field has no effect.
177  blen32:
178    type: boolean
179    description: |
180      AXI Burst Length 32.
181      When this enabled and the mixed_burst is disabled, the AXI master
182      can select a burst length of 32 on the AXI interface.
183      When the mixed_burst enabled, enabling this field has no effect.
184  blen64:
185    type: boolean
186    description: |
187      AXI Burst Length 64.
188      When this enabled and the mixed_burst is disabled, the AXI master
189      can select a burst length of 64 on the AXI interface.
190      When the mixed_burst enabled, enabling this field has no effect.
191  blen128:
192    type: boolean
193    description: |
194      AXI Burst Length 128.
195      When this enabled and the mixed_burst is disabled, the AXI master
196      can select a burst length of 128 on the AXI interface.
197      When the mixed_burst enabled, enabling this field has no effect.
198  blen256:
199    type: boolean
200    description: |
201      AXI Burst Length 256.
202      When this enabled and the mixed_burst is disabled, the AXI master
203      can select a burst length of 256 on the AXI interface.
204      When the mixed_burst enabled, enabling this field has no effect.
205  aal:
206    type: boolean
207    description: |
208      Address-Aligned Beats.
209      When this is enabled, the AXI master performs address-aligned
210      burst transfers on Read and Write channels.
211  eame:
212    type: boolean
213    description: |
214      Enhanced Address Mode Enable.
215      DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode).
216      In this mode, the DMA engine uses either the 40-bit or 48-bit address, depending
217      on the configuration.
218  dma-ch-mss:
219    type: int
220    default: 4096
221    description: |
222      Maximum Segment Size.
223      This field specifies the maximum segment size that must be
224      used while segmenting the Transmit packet. This field is valid
225      only if the TSE enabled.
226  dma-ch-tdrl:
227    type: int
228    default: 512
229    description: |
230      Transmit Descriptor Ring Length.
231      This field sets the maximum number of Tx descriptors in the
232      circular descriptor ring. The maximum number of descriptors is
233      limited to 16384 descriptors.
234  dma-ch-rdrl:
235    type: int
236    default: 512
237    description: |
238      Receive Descriptor Ring Length.
239      This field sets the maximum number of Rx descriptors in the
240      circular descriptor ring. The maximum number of descriptors is
241      limited to 16384 descriptors.
242  dma-ch-rbsz:
243    type: int
244    default: 16383
245    description: |
246      Receive Buffer size.
247      This field indicates the size of the Rx buffers specified in bytes
248      allocated by the software to store the packets the Rx DMA
249      transfers to the host memory. The maximum buffer size is
250      limited to 16K bytes. The buffer size is applicable to payload
251      buffers when split headers are enabled.
252  dma-ch-arbs:
253    type: int
254    default: 0
255    description: |
256      Alternate Receive Buffer Size
257      Indicates size in bytes for Buffer 1 when ARBS is set
258      to a non-zero value (when split header(SPH) feature is not enabled).
259      When split header feature is enabled, ARBS indicates the
260      buffer size for header data. The maximum alternate buffer is
261      limited to 1016 or 1008-bytes depending on the data bus
262      widths (64-bit or 128-bit respectively). When ARBS=0, Rx
263      Buffer1 and Rx Buffer2 sizes are based on RBSZ field. Width of
264      ARBS field is 7 or 6-bits depending on the data bus widths
265      (64-bit or 128-bit respectively).
266  dma-ch-rxpbl:
267    type: int
268    default: 32
269    description: |
270      Receive Programmable Burst Length.
271      These field indicate the maximum number of beats to be
272      transferred in one DMA data transfer.
273  dma-ch-txpbl:
274    type: int
275    default: 32
276    description: |
277      Transmit   Programmable Burst Length.
278      These field indicate the maximum number of beats to be
279      transferred in one DMA data transfer.
280  dma-ch-sph:
281    type: boolean
282    description: |
283      Header-Payload Split.
284      When this field is set, the DMA splits the header and payload in
285      the Receive path. The DMA writes the header to the Buffer
286      Address1. The DMA writes the payload to the buffer to which
287      the Buffer Address2 is pointing.
288      The software must ensure that the header fits into the Receive
289      buffers. If the header length exceeds the receive buffer size,
290      the DMA does not split the header and payload.
291  dma-ch-edse:
292    type: boolean
293    description: |
294      Enhanced Descriptor Enable.
295      When this field is set, the corresponding channel uses
296      enhanced Descriptors.
297  dma-ch-tse:
298    type: boolean
299    description: |
300      TCP Segmentation Enabled.
301      When this field is set, the DMA performs the TCP segmentation
302      for packets in Channel. The TCP segmentation is done only
303      for those packets for which the TSE is set in the Tx Normal
304      descriptor.
305  dma-ch-osp:
306    type: boolean
307    description: |
308      Operate on Second Packet.
309      When this field is set, it instructs the DMA to process the second
310      packet of the Transmit data even before closing the descriptor
311      of the first packet.
312  mtl-raa:
313    type: boolean
314    description: |
315      Receive Arbitration Algorithm.
316      This field is used to select the arbitration algorithm for the Rx
317      side. 0: Strict Priority (SP), 1: Weighted Strict Priority (WSP)
318  mtl-etsalg:
319    type: int
320    default: 0
321    description: |
322      ETS Algorithm.
323      This field selects the type of ETS algorithm to be applied for
324      traffic classes whose transmission selection algorithm (TSA) is
325      set to ETS:
326      0: WRR algorithm
327      1: WFQ algorithm
328      2: DWRR algorithm
329  rxq-dyn-dma-en:
330    type: int
331    default: 1
332    description: |
333      Receive Queue Enabled for Dynamic DMA Channel Selection.
334      Each bit position of this field maps to a queue. there are total 8 queues
335  rxq-dma-ch-sel:
336    type: uint8-array
337    default: [0, 1, 2, 3, 4, 5, 6, 7]
338    description: |
339      Receive Queue Mapped to DMA Channel. this field does not have
340      effect when rxQ-DynDma-En is enabled.
341      range 0 - 7
342  txq-size:
343    type: uint8-array
344    default: [127]
345    description: |
346      This field indicates the size of the allocated Transmit queues
347      in blocks of 256 bytes. = (txQ-size + 1) x 256
348      range: 0 - 7
349  map-queue-tc:
350    type: uint8-array
351    default: [0]
352    description: |
353      Queue to Traffic Class Mapping. range 0 - 7
354  tx-threshold-ctrl:
355    type: uint8-array
356    default: [0]
357    description: |
358          Transmit Threshold Control.
359          These field control the threshold level of the MTL Tx Queue.
360          Transmission starts when the packet size within the MTL Tx
361          Queue is larger than the threshold. In addition, full packets
362          with length less than the threshold are also transmitted. This
363          field us used only when Transmit Store and Forward is disabled.
364          range 0 - 7
365                0: 64
366                1: reserved
367                2: 96
368                3: 128
369                4: 192
370                5: 256
371                6: 384
372                7: 512
373  rx-threshold-ctrl:
374    type: uint8-array
375    default: [0]
376    description: |
377          The received packet is transferred to the application or DMA
378          when the packet size within the MTL Rx queue is larger than
379          the threshold. In addition, full packets with length less than the
380          threshold are automatically transferred. The value of 11 is not
381          applicable if the size of the configured Rx Queue is 128 bytes.
382          This field is valid only when the RSF bit is zero. This field is
383          ignored when the RSF field is set to 1.
384          range 0 - 3
385                0: 64
386                1: reserved
387                2: 96
388                3: 128
389  rxq-size:
390    type: uint8-array
391    default: [127]
392    description: |
393      Receive Queue Size. This field indicates the size of the allocated
394      Receive queues in blocks 256 bytes. = (rxQ-size + 1) x 256
395      Range: 0 - 127 ,
396  tx-store-fwrd-en:
397    type: int
398    default: 255
399    description: |
400      Transmit Store and Forward. When this field is set, the transmission
401      starts when a full packet resides in the MTL Tx Queue.
402      Each bit position of this field maps to a queue. there are total 8 queues
403  hfc-en:
404    type: int
405    default: 0
406    description: |
407      Enable Hardware Flow Control. When this field is set, the flow control
408      signal operation, based on the fill-level of Rx queue, is enabled.
409      Each bit position of this field maps to a queue. there are total 8 queues
410  cs-error-pkt-drop-dis:
411    type: int
412    default: 0
413    description: |
414      Disable Dropping of TCP/IP Checksum Error Packets
415      Each bit position of this field maps to a queue. there are total 8 queues
416  rx-store-fwrd-en:
417    type: int
418    default: 255
419    description: |
420      Receive Store and Forward. When this field is set, DWC_xgmac reads a
421      packet from the Rx queue only after the complete packet has been written to it.
422      Each bit position of this field maps to a queue. there are total 8 queues
423  fep-en:
424    type: int
425    default: 0
426    description: |
427      Forward Error Packets.  When this bit is set, all packets except the runt error
428      packets are forwarded to the application or DMA.
429      Each bit position of this field maps to a queue. there are total 8 queues
430  fup-en:
431    type: int
432    default: 0
433    description: |
434      Forward Undersized Good Packets. When this field is set, the Rx queue forwards
435      the undersized good packets.
436      Each bit position of this field maps to a queue. there are total 8 queues
437  priorities-map-tc:
438    type: array
439    default: [0]
440    description: |
441      Priorities Mapped to Traffic Class. This field determines if the transmit
442      queues associated with the traffic class should be blocked from transmitting
443      for the specified pause time when a PFC packet is received with priorities
444      matching the priorities programmed in this field.
445      range: 0 - 7 and max array size is 8
446      ex: <0,1,2,3,4,5,6,7>
447  tx-sel-algorithm:
448    type: uint8-array
449    default: [0]
450    description: |
451      Transmission Selection Algorithm. This field is used to assign a transmission
452      selection algorithm for this traffic class.
453      range: 0 -strict priority
454             1 - Credit based shaper
455             2 - Enhanced Transmission Selection
456  jumbo-pkt-en:
457    type: boolean
458    description: |
459      Jumbo Packet Enable.
460      When this bit is set, the MAC allows jumbo packets of 9018
461      bytes (9022 bytes for VLAN tagged packets) without reporting
462      a giant packet error in the Rx packet status
463  gaint-pkt-size-limit:
464    type: int
465    default: 9018
466    description: |
467      Giant Packet Size Limit.
468      If the received packet size is greater than the value
469      programmed in this field in units of bytes, the MAC declares
470      the received packet as Giant packet. The value programmed in
471      this field must be greater than or equal to 1518 bytes. Any
472      other programmed value is considered as 1518 bytes.
473