Lines Matching +full:master +full:- +full:can +full:- +full:reg
2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f411-plli2s-clock";
21 #clock-cells = <0>;
22 compatible = "st,stm32-clock-mux";
29 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
31 pinctrl: pin-controller@40020000 {
32 reg = <0x40020000 0x1c00>;
35 compatible = "st,stm32-gpio";
36 gpio-controller;
37 #gpio-cells = <2>;
38 reg = <0x40021400 0x400>;
43 compatible = "st,stm32-gpio";
44 gpio-controller;
45 #gpio-cells = <2>;
46 reg = <0x40021800 0x400>;
52 compatible = "st,stm32-usart", "st,stm32-uart";
53 reg = <0x40004800 0x400>;
61 compatible = "st,stm32-spi";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0x40003c00 0x400>;
71 compatible = "st,stm32-spi";
72 #address-cells = <1>;
73 #size-cells = <0>;
74 reg = <0x40013400 0x400>;
81 compatible = "st,stm32-i2s";
82 #address-cells = <1>;
83 #size-cells = <0>;
84 reg = <0x40013400 0x400>;
89 dma-names = "tx", "rx";
94 compatible = "st,stm32-timers";
95 reg = <0x40001400 0x400>;
99 interrupt-names = "global";
104 compatible = "st,stm32-counter";
110 compatible = "st,stm32-timers";
111 reg = <0x40010400 0x400>;
115 interrupt-names = "brk", "up", "trgcom", "cc";
120 compatible = "st,stm32-pwm";
122 #pwm-cells = <3>;
126 compatible = "st,stm32-qdec";
128 st,input-filter-level = <NO_FILTER>;
133 compatible = "st,stm32-timers";
134 reg = <0x40001800 0x400>;
138 interrupt-names = "global";
143 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
149 compatible = "st,stm32-counter";
155 compatible = "st,stm32-timers";
156 reg = <0x40001c00 0x400>;
160 interrupt-names = "global";
165 compatible = "st,stm32-pwm";
167 #pwm-cells = <3>;
171 compatible = "st,stm32-counter";
177 compatible = "st,stm32-timers";
178 reg = <0x40002000 0x400>;
182 interrupt-names = "global";
187 compatible = "st,stm32-pwm";
189 #pwm-cells = <3>;
193 compatible = "st,stm32-counter";
199 compatible = "st,stm32-rng";
200 reg = <0x50060800 0x400>;
207 num-bidir-endpoints = <6>;
216 compatible = "st,stm32-qspi";
217 #address-cells = <0x1>;
218 #size-cells = <0x0>;
219 reg = <0xa0001000 0x400>;
225 can1: can@40006400 {
226 compatible = "st,stm32-bxcan";
227 reg = <0x40006400 0x400>;
229 interrupt-names = "TX", "RX0", "RX1", "SCE";
234 can2: can@40006800 {
235 compatible = "st,stm32-bxcan";
236 reg = <0x40006800 0x400>;
238 interrupt-names = "TX", "RX0", "RX1", "SCE";
239 /* also enabling clock for can1 (master instance) */
241 master-can-reg = <0x40006400>;
247 io-channels = <&adc1 18>;