1# Copyright (c) 2022, Basalte bv
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Atmel Static Memory Controller (SMC).
6
7  The SMC allows to interface with static-memory mapped external devices such as
8  SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
9
10  The SMC is clocked through the Master Clock (MCK) which is controlled by the
11  Power Management Controller (PMC).
12
13  The SMC controller can have up to 4 children defining the connected external
14  memory devices. The reg property is set to the device's Chip Select.
15  Device Tree example taken from the sam4_xplained board:
16
17  &smc {
18    status = "okay";
19    pinctrl-0 = <&smc_default>;
20    pinctrl-names = "default";
21
22    is66wv51216dbll@0 {
23      reg = <0>;
24
25      atmel,smc-write-mode = "nwe";
26      atmel,smc-read-mode = "nrd";
27      atmel,smc-setup-timing = <1 1 1 1>;
28      atmel,smc-pulse-timing = <6 6 6 6>;
29      atmel,smc-cycle-timing = <7 7>;
30    };
31  };
32
33  The above example configures a is66wv51216dbll-55 device. The device is a
34  low power static RAM which uses NWE and NRD signals connected to the WE
35  and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed)
36  each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
37  55ns, as per specification, it requires atmel,smc-cycle-timing of at least
38  7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
39  setup, pulse and hold. The setup is used to address the memory. The pulse
40  is the time used to read/write. The hold is used to release memory. For the
41  is66wv51216dbll-55 a minimum setup of 5ns (1 cycle) with at least 45ns
42  (6 cycles) for CPU read/write and no hold time is required.
43  Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
44  should have additional cycles to accommodate for hold values.
45
46    No Hold Time:
47    cycle-timing (7) = setup (1) + pulse (6) + hold (0)
48
49    With 3 Hold Times:
50    cycle-timing (10) = setup (1) + pulse (6) + hold (3)
51
52  Finally, in order to make the memory available you will need to define new
53  memory device/s in DeviceTree:
54
55  sram1: sram@60000000 {
56      compatible = "zephyr,memory-region", "mmio-sram";
57      device_type = "memory";
58      reg = <0x60000000 DT_SIZE_K(512)>;
59      zephyr,memory-region = "SRAM1";
60  };
61
62compatible: "atmel,sam-smc"
63
64include: [base.yaml, pinctrl-device.yaml]
65
66properties:
67  reg:
68    required: true
69
70  clocks:
71    required: true
72
73  "#address-cells":
74    required: true
75    const: 1
76
77  "#size-cells":
78    required: true
79    const: 0
80
81child-binding:
82  description: |
83    Child device nodes are representing devices connected to the EBI/SMC bus.
84
85  properties:
86    reg:
87      type: int
88      required: true
89      description: |
90        The device's SMC Chip Select number.
91        Valid range: 0 - 3
92
93    atmel,smc-write-mode:
94      type: string
95      required: true
96      description: |
97        Select which signal is used for the write operation, either the chip
98        select (ncs) or a dedicated write enable pin (nwe). The data is put
99        on the bus during the pulse and hold steps of that signal.
100        The internal data buffers are switched to output mode after the NCS_WR
101        or NWE setup time.
102      enum:
103        - "ncs"
104        - "nwe"
105
106    atmel,smc-read-mode:
107      type: string
108      required: true
109      description: |
110        Select which signal is used for the read operation, either the chip
111        select (ncs) or a dedicated output enable pin (nrd). The data is read
112        from the bus during the pulse and hold steps of that signal.
113      enum:
114        - "ncs"
115        - "nrd"
116
117    atmel,smc-setup-timing:
118      type: array
119      required: true
120      description: |
121        This value is used to setup memory region (set address). The setup
122        values is an array of the signals NWE, NCS_WR, NRD and NCS_RD
123        where each value is configured in terms of MCK cycles. The SMC
124        controller allows use of setups value of 0 (no delays) when
125        consecutive reads/writes are used. Each value is encoded in
126        6 bits where the highest bit adds an offset of 128 cycles.
127        The effective value for each element is: 128 x setup[5] + setup[4:0]
128
129    atmel,smc-pulse-timing:
130      type: array
131      required: true
132      description: |
133        This value is used to effectivelly read/write at memory region (pulse phase).
134        The pulse value is an array of the signals NWE, NCS_WR, NRD and NCS_RD where
135        each value is configured in terms of MCK cycles and a value of 0 is forbidden.
136        Each value is encoded in 7 bits where the highest bit adds an offset of 256
137        cycles. The effective value for each element is: 256 x setup[6] + setup[5:0]
138
139    atmel,smc-cycle-timing:
140      type: array
141      required: true
142      description: |
143        SMC timing configurations in cycles for the total write and read
144        length respectively.
145        This value describes the entire write/read operation timing which
146        is defined as: cycle = setup + pulse + hold
147        Value has to be greater or equal to setup + pulse timing and
148        is encoded in 9 bits where the two highest bits are multiplied
149        with an offset of 256.
150        Effective value for each element: 256 x cycle[8:7] + cycle[6:0]
151