| /Zephyr-latest/dts/bindings/flash_controller/ |
| D | st,stm32wb-flash-controller.yaml | 1 description: STM32 WB flash controller
3 compatible: "st,stm32wb-flash-controller"
5 include: flash-controller.yaml
8 single-bank:
10 description: dual-bank mode not enabled (page erase 4096k)
12 dual-bank:
14 description: dual-bank mode enabled (page erase 2048k)
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| D | st,stm32-xspi-nor.yaml | 1 # Copyright (c) 2021 - 2024 STMicroelectronics
2 # SPDX-License-Identifier: Apache-2.0
5 STM32 XSPI Flash controller supporting the JEDEC CFI interface
7 Representation of a serial flash on a xspi bus:
9 mx25lm51245: xspi-nor-flash@70000000 {
10 compatible = "st,stm32-xspi-nor";
12 data-mode = <XSPI_OCTO_MODE>; /* access on 8 data lines */
13 data-rate = <XSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-xspi-nor"
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| D | st,stm32-ospi-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 OSPI Flash controller supporting the JEDEC CFI interface
7 Representation of a serial flash on a octospi bus:
9 mx25lm51245: ospi-nor-flash@70000000 {
10 compatible = "st,stm32-ospi-nor";
12 data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-ospi-nor"
20 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
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| D | nuvoton,npcx-fiu-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The SPI NOR flash devices accessed by Nuvoton Flash Interface Unit (FIU).
7 Representation of a SPI NOR flash on a qspi bus looks like:
10 compatible ="nuvoton,npcx-fiu-nor";
14 qspi-flags = <NPCX_QSPI_SW_CS1>;
15 mapped-addr = <0x64000000>;
16 pinctrl-0 = <&int_flash_sl>;
17 pinctrl-names = "default";
20 compatible: "nuvoton,npcx-fiu-nor"
22 include: [flash-controller.yaml, pinctrl-device.yaml, "jedec,spi-nor-common.yaml"]
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| /Zephyr-latest/drivers/flash/ |
| D | Kconfig.renesas_ra | 4 # SPDX-License-Identifier: Apache-2.0
7 bool "RA flash driver"
17 Enable flash driver for RA series
22 bool "Extended operation for flash write protection control"
25 Enables flash extended operation to enable/disable flash write
29 bool "Dual bank mode"
31 Enable dual bank mode
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| D | flash_stm32l4x.c | 6 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/drivers/flash.h>
38 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
39 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
43 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
44 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
45 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
48 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
49 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
54 regs->ACR |= FLASH_ACR_ICRST; in flush_cache()
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| D | Kconfig.nxp_s32 | 2 # SPDX-License-Identifier: Apache-2.0
14 Enable the Flash driver for a NOR Serial Flash Memory device connected
20 bool "Read flash parameters at runtime"
22 Read flash device characteristics from the device at runtime.
24 JESD216-compatible devices, with the following notes:
25 - Quad Enable Requirements bitfield (DW15) must be present in the SFDP
26 tables to configure Quad mode. Otherwise it defaults to Dual or
28 - Soft Reset bitfield (DW16) must be present in the SFDP tables to
30 - 0-X-X mode discovery not yet implemented by the HAL.
34 device size and jedec-id properties must be set in devicetree node.
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| D | flash_stm32f7x.c | 5 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/flash.h>
29 if (regs->ACR & FLASH_ACR_ARTEN) { in flush_cache()
30 regs->ACR &= ~FLASH_ACR_ARTEN; in flush_cache()
35 regs->ACR |= FLASH_ACR_ARTRST; in flush_cache()
36 regs->ACR &= ~FLASH_ACR_ARTRST; in flush_cache()
37 regs->ACR |= FLASH_ACR_ARTEN; in flush_cache()
47 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
48 return -EIO; in write_byte()
57 regs->CR = (regs->CR & CR_PSIZE_MASK) | in write_byte()
[all …]
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| /Zephyr-latest/dts/bindings/qspi/ |
| D | st,stm32-qspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
14 dma-names = "tx_rx";
19 compatible: "st,stm32-qspi"
21 include: [base.yaml, pinctrl-device.yaml]
32 pinctrl-0:
35 pinctrl-names:
55 dma-names:
60 dma-names = "tx_rx";
62 dual-flash:
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| /Zephyr-latest/samples/subsys/usb_c/sink/ |
| D | README.rst | 1 .. zephyr:code-sample:: usb-c-sink
2 :name: Basic USB-C Sink
3 :relevant-api: _usbc_device_api
5 Implement a USB-C Power Delivery application in the form of a USB-C Sink.
10 This example demonstrates how to create a USB-C Power Delivery application and
11 how to generate USB VIF policies in XML format using the USB-C subsystem. The
12 application implements a USB-C Sink device.
14 After the USB-C Sink device is plugged into a Power Delivery charger, it
18 .. _usb-c-sink-sample-requirements:
23 node that's compatible with ``usb-c-connector``.
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| /Zephyr-latest/boards/others/candlelightfd/ |
| D | candlelightfd_stm32g0b1xx_dual.yaml | 1 identifier: candlelightfd/stm32g0b1xx/dual
2 name: candleLightFD Dual
6 - zephyr
7 - gnuarmemb
9 flash: 128
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| /Zephyr-latest/soc/nuvoton/npcx/ |
| D | Kconfig | 1 # Nuvoton Cortex-M4 Embedded Controller
4 # SPDX-License-Identifier: Apache-2.0
11 On NPCX series chip, the NPCX ROM code loads firmware image from flash
44 prompt "Clock rate to use for SPI flash"
48 binary from flash to RAM.
51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
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| /Zephyr-latest/soc/infineon/cat1a/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
32 bool "Dual-core support [activate Cortex-M4]"
35 Cortex-M0 CPU should boot Cortex-M4
42 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6
43 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
48 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE
49 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
50 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
13 On Microchip MEC series chip, the ROM code loads firmware image from flash
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
30 prompt "Clock rate to use for SPI flash"
34 firmware binary from flash to RAM.
37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
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| /Zephyr-latest/soc/nxp/imxrt/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
15 # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
24 application from an external flash device.
58 flash devices including read command sequence, quad mode enablement
60 parameter to be presented in serial nor flash.
117 bool "Dual core operation on the RT11xx series"
121 in dual core mode. Enables dual core operation on the RT11xx series,
122 by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
123 The M4 image will be loaded from flash into RAM based off a
151 MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
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| /Zephyr-latest/boards/sipeed/longan_nano/support/ |
| D | openocd.cfg | 2 # SPDX-License-Identifier: Apache-2.0
6 ftdi_device_desc "Dual RS232"
7 #ftdi_device_desc "Sipeed-Debug"
14 ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
19 proc gd32vf103-pre-load {} {
23 proc gd32vf103-load {file} {
24 flash protect 0 0 last off
25 flash write_image erase $file
29 proc gd32vf103-post-verify {} {
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4250b/ |
| D | slwrb4250b.yaml | 2 name: EFR32FG 2400/868 MHz 13 dBm Dual Band Radio Board (SLWRB4250B, BRD4250B)
6 flash: 256
8 - zephyr
9 - gnuarmemb
10 - xtools
12 - counter
13 - gpio
14 - nvs
15 - spi
16 - uart
[all …]
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4170a/ |
| D | slwrb4170a.yaml | 2 name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band Radio Board (SLWRB4170A, BRD4170A)
6 flash: 1024
8 - zephyr
9 - gnuarmemb
11 - counter
12 - gpio
13 - nvs
14 - spi
15 - uart
16 - watchdog
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| /Zephyr-latest/boards/silabs/radio_boards/slwrb4255a/ |
| D | slwrb4255a.yaml | 2 name: EFR32FG13 2400/915 MHz 19 dBm Dual Band Radio Board (SLWRB4255A, BRD4255A)
6 flash: 512
8 - zephyr
9 - gnuarmemb
10 - xtools
12 - counter
13 - gpio
14 - nvs
15 - spi
16 - uart
[all …]
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| /Zephyr-latest/boards/sifive/hifive1/support/ |
| D | openocd.cfg | 4 ftdi device_desc "Dual RS232-HS"
7 ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
10 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
13 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
14 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
16 flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
18 proc hifive1-load {file} {
19 flash protect 0 64 last off
20 flash write_image erase $file
23 proc hifive1-reset-halt {} {
[all …]
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| /Zephyr-latest/samples/subsys/nvs/boards/ |
| D | nucleo_wb55rg.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &storage_partition;
11 /* Set 12KB of storage at the end of 1st half of flash (dual core constraints) */
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | nordic,qspi-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 QSPI NOR flash supporting the JEDEC CFI interface.
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
[all …]
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| /Zephyr-latest/tests/boards/mec172xevb_assy6906/qspi/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
90 * dual: 4 clocks per byte
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
210 * - Find spi device
211 * - Read flash jedec id
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | Kconfig.defconfig | 2 # SPDX-License-Identifier: Apache-2.0
15 # in dual core mode.
20 DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
22 # Move the LMA for the second core image to be in the flash region of primary
23 # core, so that JLink flash will load it correctly.
60 depends on FLASH
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| /Zephyr-latest/soc/nxp/mcx/mcxn/ |
| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
39 in dual core mode.
42 bool "Disable the CACHE64 cache for FlexSPI flash accesses"
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