5  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/flash.h>
29 	if (regs->ACR & FLASH_ACR_ARTEN) {  in flush_cache()
30 		regs->ACR &= ~FLASH_ACR_ARTEN;  in flush_cache()
35 		regs->ACR |= FLASH_ACR_ARTRST;  in flush_cache()
36 		regs->ACR &= ~FLASH_ACR_ARTRST;  in flush_cache()
37 		regs->ACR |= FLASH_ACR_ARTEN;  in flush_cache()
47 	if (regs->CR & FLASH_CR_LOCK) {  in write_byte()
48 		return -EIO;  in write_byte()
57 	regs->CR = (regs->CR & CR_PSIZE_MASK) |  in write_byte()
68 	regs->CR &= (~FLASH_CR_PG);  in write_byte()
79 	if (regs->CR & FLASH_CR_LOCK) {  in erase_sector()
80 		return -EIO;  in erase_sector()
88 	/* Dual bank mode, SNB MSB selects the bank2,  in erase_sector()
103 	regs->CR = (regs->CR & ~(FLASH_CR_PSIZE | FLASH_CR_SNB)) |  in erase_sector()
112 	regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);  in erase_sector()
131 	rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);  in flash_stm32_block_erase_loop()
168 	if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {  in flash_stm32_option_bytes_write()
169 		return -EIO;  in flash_stm32_option_bytes_write()
172 	if ((regs->OPTCR & mask) == value) {  in flash_stm32_option_bytes_write()
181 	regs->OPTCR = (regs->OPTCR & ~mask) | value;  in flash_stm32_option_bytes_write()
182 	regs->OPTCR |= FLASH_OPTCR_OPTSTRT;  in flash_stm32_option_bytes_write()
194 	return regs->OPTCR;  in flash_stm32_option_bytes_read()
202 	return (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;  in flash_stm32_get_rdp_level()
212 /* Some SoC can run in single or dual bank mode, others can't.
213  * Different SoC flash layouts are specified in various reference
214  * manuals, but the flash layout for a given number of sectors is
217  * FLASH_SECTOR_TOTAL have different flash size.
222  * in single or dual bank mode.
225 #error "Unknown flash layout"
260 	/* RM0410, table 4: STM32F76xxx and STM32F77xxx in dual bank */
269 #error "Unknown flash layout"
277 	if (FLASH_STM32_REGS(dev)->OPTCR & FLASH_OPTCR_nDBANK) {  in flash_stm32_page_layout()