1 /*
2 * Copyright (c) 2018 Aurelien Jarno
3 * Copyright (c) 2018 Yong Jin
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/kernel.h>
9 #include <zephyr/device.h>
10 #include <string.h>
11 #include <zephyr/drivers/flash.h>
12 #include <zephyr/init.h>
13 #include <zephyr/sys/barrier.h>
14 #include <soc.h>
15
16 #include "flash_stm32.h"
17
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)18 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
19 uint32_t len,
20 bool write)
21 {
22 ARG_UNUSED(write);
23
24 return flash_stm32_range_exists(dev, offset, len);
25 }
26
flush_cache(FLASH_TypeDef * regs)27 static inline void flush_cache(FLASH_TypeDef *regs)
28 {
29 if (regs->ACR & FLASH_ACR_ARTEN) {
30 regs->ACR &= ~FLASH_ACR_ARTEN;
31 /* Reference manual:
32 * The ART cache can be flushed only if the ART accelerator
33 * is disabled (ARTEN = 0).
34 */
35 regs->ACR |= FLASH_ACR_ARTRST;
36 regs->ACR &= ~FLASH_ACR_ARTRST;
37 regs->ACR |= FLASH_ACR_ARTEN;
38 }
39 }
40
write_byte(const struct device * dev,off_t offset,uint8_t val)41 static int write_byte(const struct device *dev, off_t offset, uint8_t val)
42 {
43 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
44 int rc;
45
46 /* if the control register is locked, do not fail silently */
47 if (regs->CR & FLASH_CR_LOCK) {
48 return -EIO;
49 }
50
51 rc = flash_stm32_wait_flash_idle(dev);
52 if (rc < 0) {
53 return rc;
54 }
55
56 /* prepare to write a single byte */
57 regs->CR = (regs->CR & CR_PSIZE_MASK) |
58 FLASH_PSIZE_BYTE | FLASH_CR_PG;
59 /* flush the register write */
60 barrier_dsync_fence_full();
61
62 /* write the data */
63 *((uint8_t *) offset + FLASH_STM32_BASE_ADDRESS) = val;
64 /* flush the register write */
65 barrier_dsync_fence_full();
66
67 rc = flash_stm32_wait_flash_idle(dev);
68 regs->CR &= (~FLASH_CR_PG);
69
70 return rc;
71 }
72
erase_sector(const struct device * dev,uint32_t sector)73 static int erase_sector(const struct device *dev, uint32_t sector)
74 {
75 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
76 int rc;
77
78 /* if the control register is locked, do not fail silently */
79 if (regs->CR & FLASH_CR_LOCK) {
80 return -EIO;
81 }
82
83 rc = flash_stm32_wait_flash_idle(dev);
84 if (rc < 0) {
85 return rc;
86 }
87
88 /* Dual bank mode, SNB MSB selects the bank2,
89 * others select sector, so we remap sector number.
90 */
91 #if defined(FLASH_OPTCR_nDBANK) && FLASH_SECTOR_TOTAL == 24
92 #if CONFIG_FLASH_SIZE == 2048
93 if (sector > 11) {
94 sector += 4U;
95 }
96 #elif CONFIG_FLASH_SIZE == 1024
97 if (sector > 7) {
98 sector += 8U;
99 }
100 #endif /* CONFIG_FLASH_SIZE */
101 #endif /* defined(FLASH_OPTCR_nDBANK) && FLASH_SECTOR_TOTAL == 24 */
102
103 regs->CR = (regs->CR & ~(FLASH_CR_PSIZE | FLASH_CR_SNB)) |
104 FLASH_PSIZE_BYTE |
105 FLASH_CR_SER |
106 (sector << FLASH_CR_SNB_Pos) |
107 FLASH_CR_STRT;
108 /* flush the register write */
109 barrier_dsync_fence_full();
110
111 rc = flash_stm32_wait_flash_idle(dev);
112 regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
113
114 return rc;
115 }
116
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)117 int flash_stm32_block_erase_loop(const struct device *dev,
118 unsigned int offset,
119 unsigned int len)
120 {
121 struct flash_pages_info info;
122 uint32_t start_sector, end_sector;
123 uint32_t i;
124 int rc = 0;
125
126 rc = flash_get_page_info_by_offs(dev, offset, &info);
127 if (rc) {
128 return rc;
129 }
130 start_sector = info.index;
131 rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);
132 if (rc) {
133 return rc;
134 }
135 end_sector = info.index;
136
137 for (i = start_sector; i <= end_sector; i++) {
138 rc = erase_sector(dev, i);
139 if (rc < 0) {
140 break;
141 }
142 }
143
144 return rc;
145 }
146
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)147 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
148 const void *data, unsigned int len)
149 {
150 int i, rc = 0;
151
152 for (i = 0; i < len; i++, offset++) {
153 rc = write_byte(dev, offset, ((const uint8_t *) data)[i]);
154 if (rc < 0) {
155 return rc;
156 }
157 }
158
159 return rc;
160 }
161
flash_stm32_option_bytes_write(const struct device * dev,uint32_t mask,uint32_t value)162 int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
163 uint32_t value)
164 {
165 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
166 int rc;
167
168 if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
169 return -EIO;
170 }
171
172 if ((regs->OPTCR & mask) == value) {
173 return 0;
174 }
175
176 rc = flash_stm32_wait_flash_idle(dev);
177 if (rc < 0) {
178 return rc;
179 }
180
181 regs->OPTCR = (regs->OPTCR & ~mask) | value;
182 regs->OPTCR |= FLASH_OPTCR_OPTSTRT;
183
184 /* Make sure previous write is completed. */
185 barrier_dsync_fence_full();
186
187 return flash_stm32_wait_flash_idle(dev);
188 }
189
flash_stm32_option_bytes_read(const struct device * dev)190 uint32_t flash_stm32_option_bytes_read(const struct device *dev)
191 {
192 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
193
194 return regs->OPTCR;
195 }
196
197 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
flash_stm32_get_rdp_level(const struct device * dev)198 uint8_t flash_stm32_get_rdp_level(const struct device *dev)
199 {
200 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
201
202 return (regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;
203 }
204
flash_stm32_set_rdp_level(const struct device * dev,uint8_t level)205 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
206 {
207 flash_stm32_option_bytes_write(dev, FLASH_OPTCR_RDP_Msk,
208 (uint32_t)level << FLASH_OPTCR_RDP_Pos);
209 }
210 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
211
212 /* Some SoC can run in single or dual bank mode, others can't.
213 * Different SoC flash layouts are specified in various reference
214 * manuals, but the flash layout for a given number of sectors is
215 * consistent across these manuals. The number of sectors is given
216 * by the HAL as FLASH_SECTOR_TOTAL. And some SoC that with same
217 * FLASH_SECTOR_TOTAL have different flash size.
218 *
219 * In case of 8 sectors and 24 sectors we need to differentiate
220 * between two cases by using the memory size.
221 * In case of 24 sectors we need to check if the SoC is running
222 * in single or dual bank mode.
223 */
224 #ifndef FLASH_SECTOR_TOTAL
225 #error "Unknown flash layout"
226 #elif FLASH_SECTOR_TOTAL == 2
227 static const struct flash_pages_layout stm32f7_flash_layout[] = {
228 /* RM0385, table 4: STM32F750xx */
229 {.pages_count = 2, .pages_size = KB(32)},
230 };
231 #elif FLASH_SECTOR_TOTAL == 4
232 static const struct flash_pages_layout stm32f7_flash_layout[] = {
233 /* RM0431, table 4: STM32F730xx */
234 {.pages_count = 4, .pages_size = KB(16)},
235 };
236 #elif FLASH_SECTOR_TOTAL == 8
237 #if CONFIG_FLASH_SIZE == 512
238 static const struct flash_pages_layout stm32f7_flash_layout[] = {
239 /* RM0431, table 3: STM32F72xxx and STM32F732xx/F733xx */
240 {.pages_count = 4, .pages_size = KB(16)},
241 {.pages_count = 1, .pages_size = KB(64)},
242 {.pages_count = 3, .pages_size = KB(128)},
243 };
244 #elif CONFIG_FLASH_SIZE == 1024
245 static const struct flash_pages_layout stm32f7_flash_layout[] = {
246 /* RM0385, table 3: STM32F756xx and STM32F74xxx */
247 {.pages_count = 4, .pages_size = KB(32)},
248 {.pages_count = 1, .pages_size = KB(128)},
249 {.pages_count = 3, .pages_size = KB(256)},
250 };
251 #endif /* CONFIG_FLASH_SIZE */
252 #elif FLASH_SECTOR_TOTAL == 24
253 static const struct flash_pages_layout stm32f7_flash_layout_single_bank[] = {
254 /* RM0410, table 3: STM32F76xxx and STM32F77xxx in single bank */
255 {.pages_count = 4, .pages_size = KB(32)},
256 {.pages_count = 1, .pages_size = KB(128)},
257 {.pages_count = 7, .pages_size = KB(256)},
258 };
259 static const struct flash_pages_layout stm32f7_flash_layout_dual_bank[] = {
260 /* RM0410, table 4: STM32F76xxx and STM32F77xxx in dual bank */
261 {.pages_count = 4, .pages_size = KB(16)},
262 {.pages_count = 1, .pages_size = KB(64)},
263 {.pages_count = 7, .pages_size = KB(128)},
264 {.pages_count = 4, .pages_size = KB(16)},
265 {.pages_count = 1, .pages_size = KB(64)},
266 {.pages_count = 7, .pages_size = KB(128)},
267 };
268 #else
269 #error "Unknown flash layout"
270 #endif/* !defined(FLASH_SECTOR_TOTAL) */
271
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)272 void flash_stm32_page_layout(const struct device *dev,
273 const struct flash_pages_layout **layout,
274 size_t *layout_size)
275 {
276 #if FLASH_OPTCR_nDBANK
277 if (FLASH_STM32_REGS(dev)->OPTCR & FLASH_OPTCR_nDBANK) {
278 *layout = stm32f7_flash_layout_single_bank;
279 *layout_size = ARRAY_SIZE(stm32f7_flash_layout_single_bank);
280 } else {
281 *layout = stm32f7_flash_layout_dual_bank;
282 *layout_size = ARRAY_SIZE(stm32f7_flash_layout_dual_bank);
283 }
284 #else
285 ARG_UNUSED(dev);
286 *layout = stm32f7_flash_layout;
287 *layout_size = ARRAY_SIZE(stm32f7_flash_layout);
288 #endif
289 }
290
