1# Copyright (c) 2023 Nuvoton Technology Corporation.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    The SPI NOR flash devices accessed by Nuvoton Flash Interface Unit (FIU).
6
7    Representation of a SPI NOR flash on a qspi bus looks like:
8
9      int_flash: w25q40@0 {
10            compatible ="nuvoton,npcx-fiu-nor";
11            size = <DT_SIZE_K(512 * 8)>;
12            reg = <0>;
13
14            qspi-flags = <NPCX_QSPI_SW_CS1>;
15            mapped-addr = <0x64000000>;
16            pinctrl-0 = <&int_flash_sl>;
17            pinctrl-names = "default";
18      };
19
20compatible: "nuvoton,npcx-fiu-nor"
21
22include: [flash-controller.yaml, pinctrl-device.yaml, "jedec,spi-nor-common.yaml"]
23
24on-bus: qspi
25
26properties:
27  mapped-addr:
28    type: int
29    required: true
30    description: Mapped memory address of direct read access for spi nor flash.
31  max-timeout:
32    type: int
33    default: 10000
34    description: Typically, it equals to max timeout of chip erase in ms.
35  qspi-flags:
36    type: int
37    required: true
38    description: The definitions for configuring the Quad-SPI peripherals.
39  rd-mode:
40    type: string
41    default: "NPCX_RD_MODE_FAST_DUAL"
42    description: |
43      Selects the SPI read access type of Direct Read Access. Usually, we choose
44      Fast Read Dual I/O mode for better performance. If the nor spi flash does
45      not support this mode, please set this property explicitly.
46    enum:
47      - "NPCX_RD_MODE_NORMAL" # Direct read access by command code 03h
48      - "NPCX_RD_MODE_FAST" # Direct read access by command code 0bh
49      - "NPCX_RD_MODE_FAST_DUAL" # Direct read access by command code bbh
50  spi-dev-size:
51    type: string
52    description: |
53      Select the size of the address space allocated for SPI device. This affects
54      the address space for any direct flash access.
55    enum:
56      - "NPCX_SPI_DEV_SIZE_1M"
57      - "NPCX_SPI_DEV_SIZE_2M"
58      - "NPCX_SPI_DEV_SIZE_4M"
59      - "NPCX_SPI_DEV_SIZE_8M"
60      - "NPCX_SPI_DEV_SIZE_16M"
61      - "NPCX_SPI_DEV_SIZE_32M"
62      - "NPCX_SPI_DEV_SIZE_64M"
63      - "NPCX_SPI_DEV_SIZE_128M"
64