1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS
4 * Copyright (c) 2019 Centaur Analytics, Inc
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define LOG_DOMAIN flash_stm32l4
10 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(LOG_DOMAIN);
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <string.h>
17 #include <zephyr/drivers/flash.h>
18 #include <zephyr/sys/barrier.h>
19 #include <zephyr/init.h>
20 #include <soc.h>
21
22 #include "flash_stm32.h"
23
24 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && \
25 !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) && \
26 !defined(STM32L4Q5xx) && !defined(STM32L4P5xx)
27 #define STM32L4X_PAGE_SHIFT 11
28 #else
29 #define STM32L4X_PAGE_SHIFT 12
30 #endif
31
32 #if defined(FLASH_OPTR_DUALBANK) || defined(FLASH_STM32_DBANK)
33 #define CONTROL_DCACHE
34 #endif
35
flush_cache(FLASH_TypeDef * regs)36 static inline void flush_cache(FLASH_TypeDef *regs)
37 {
38 if (regs->ACR & FLASH_ACR_DCEN) {
39 regs->ACR &= ~FLASH_ACR_DCEN;
40 /* Datasheet: DCRST: Data cache reset
41 * This bit can be written only when the data cache is disabled
42 */
43 regs->ACR |= FLASH_ACR_DCRST;
44 regs->ACR &= ~FLASH_ACR_DCRST;
45 regs->ACR |= FLASH_ACR_DCEN;
46 }
47
48 if (regs->ACR & FLASH_ACR_ICEN) {
49 regs->ACR &= ~FLASH_ACR_ICEN;
50 /* Datasheet: ICRST: Instruction cache reset :
51 * This bit can be written only when the instruction cache
52 * is disabled
53 */
54 regs->ACR |= FLASH_ACR_ICRST;
55 regs->ACR &= ~FLASH_ACR_ICRST;
56 regs->ACR |= FLASH_ACR_ICEN;
57 }
58 }
59
60 /*
61 * STM32L4xx devices can have up to 512 2K pages on two 256x2K pages banks
62 *
63 * STM32L4R/Sxx devices can have up to 512 4K pages on two 256x4K pages banks
64 */
get_page(off_t offset)65 static unsigned int get_page(off_t offset)
66 {
67 return offset >> STM32L4X_PAGE_SHIFT;
68 }
69
write_dword(const struct device * dev,off_t offset,uint64_t val)70 static int write_dword(const struct device *dev, off_t offset, uint64_t val)
71 {
72 volatile uint32_t *flash = (uint32_t *)(offset + FLASH_STM32_BASE_ADDRESS);
73 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
74 #ifdef CONTROL_DCACHE
75 bool dcache_enabled = false;
76 #endif /* CONTROL_DCACHE */
77 uint32_t tmp;
78 int rc;
79
80 /* if the control register is locked, do not fail silently */
81 if (regs->CR & FLASH_CR_LOCK) {
82 return -EIO;
83 }
84
85 /* Check that no Flash main memory operation is ongoing */
86 rc = flash_stm32_wait_flash_idle(dev);
87 if (rc < 0) {
88 return rc;
89 }
90
91 /* Check if this double word is erased and value isn't 0.
92 *
93 * It is allowed to write only zeros over an already written dword
94 * See 3.3.7 in reference manual.
95 */
96 if ((flash[0] != 0xFFFFFFFFUL ||
97 flash[1] != 0xFFFFFFFFUL) && val != 0UL) {
98 LOG_ERR("Word at offs %ld not erased", (long)offset);
99 return -EIO;
100 }
101
102 #ifdef CONTROL_DCACHE
103 /*
104 * Disable the data cache to avoid the silicon errata 2.2.3:
105 * "Data cache might be corrupted during Flash memory read-while-write operation"
106 */
107 if (regs->ACR & FLASH_ACR_DCEN) {
108 dcache_enabled = true;
109 regs->ACR &= (~FLASH_ACR_DCEN);
110 }
111 #endif /* CONTROL_DCACHE */
112
113 /* Set the PG bit */
114 regs->CR |= FLASH_CR_PG;
115
116 /* Flush the register write */
117 tmp = regs->CR;
118
119 /* Perform the data write operation at the desired memory address */
120 flash[0] = (uint32_t)val;
121 flash[1] = (uint32_t)(val >> 32);
122
123 /* Wait until the BSY bit is cleared */
124 rc = flash_stm32_wait_flash_idle(dev);
125
126 /* Clear the PG bit */
127 regs->CR &= (~FLASH_CR_PG);
128
129 #ifdef CONTROL_DCACHE
130 /* Reset/enable the data cache if previously enabled */
131 if (dcache_enabled) {
132 regs->ACR |= FLASH_ACR_DCRST;
133 regs->ACR &= (~FLASH_ACR_DCRST);
134 regs->ACR |= FLASH_ACR_DCEN;
135 }
136 #endif /* CONTROL_DCACHE */
137
138 return rc;
139 }
140
141 #define SOC_NV_FLASH_SIZE DT_REG_SIZE(DT_INST(0, soc_nv_flash))
142
erase_page(const struct device * dev,unsigned int page)143 static int erase_page(const struct device *dev, unsigned int page)
144 {
145 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
146 uint32_t tmp;
147 uint16_t pages_per_bank;
148 int rc;
149
150 #if !defined(FLASH_OPTR_DUALBANK) && !defined(FLASH_STM32_DBANK)
151 /* Single bank device. Each page is of 2KB size */
152 pages_per_bank = SOC_NV_FLASH_SIZE >> 11;
153 #elif defined(FLASH_OPTR_DUALBANK)
154 /* L4 series (2K page size) with configurable Dual Bank (default y) */
155 /* Dual Bank is only option for 1M devices */
156 if ((regs->OPTR & FLASH_OPTR_DUALBANK) ||
157 (SOC_NV_FLASH_SIZE == (1024*1024))) {
158 /* Dual Bank configuration (nbr pages = flash size / 2 / 2K) */
159 pages_per_bank = SOC_NV_FLASH_SIZE >> 12;
160 } else {
161 /* Single bank configuration. This has not been validated. */
162 /* Not supported for now. */
163 return -ENOTSUP;
164 }
165 #elif defined(FLASH_STM32_DBANK)
166 /* L4+ series (4K page size) with configurable Dual Bank (default y)*/
167 if (regs->OPTR & FLASH_STM32_DBANK) {
168 /* Dual Bank configuration (nbre pags = flash size / 2 / 4K) */
169 pages_per_bank = SOC_NV_FLASH_SIZE >> 13;
170 } else {
171 /* Single bank configuration */
172 /* Requires 128 bytes data read. This config is not supported */
173 return -ENOTSUP;
174 }
175 #endif
176
177 /* if the control register is locked, do not fail silently */
178 if (regs->CR & FLASH_CR_LOCK) {
179 return -EIO;
180 }
181
182 /* Check that no Flash memory operation is ongoing */
183 rc = flash_stm32_wait_flash_idle(dev);
184 if (rc < 0) {
185 return rc;
186 }
187
188 flush_cache(regs);
189
190 /* Set the PER bit and select the page you wish to erase */
191 regs->CR |= FLASH_CR_PER;
192 #ifdef FLASH_CR_BKER
193 regs->CR &= ~FLASH_CR_BKER_Msk;
194 /* Select bank, only for DUALBANK devices */
195 if (page >= pages_per_bank) {
196 regs->CR |= FLASH_CR_BKER;
197 }
198 #endif
199 regs->CR &= ~FLASH_CR_PNB_Msk;
200 regs->CR |= ((page % pages_per_bank) << 3);
201
202 /* Set the STRT bit */
203 regs->CR |= FLASH_CR_STRT;
204
205 /* flush the register write */
206 tmp = regs->CR;
207
208 /* Wait for the BSY bit */
209 rc = flash_stm32_wait_flash_idle(dev);
210
211 regs->CR &= ~FLASH_CR_PER;
212
213 return rc;
214 }
215
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)216 int flash_stm32_block_erase_loop(const struct device *dev,
217 unsigned int offset,
218 unsigned int len)
219 {
220 int i, rc = 0;
221
222 i = get_page(offset);
223 for (; i <= get_page(offset + len - 1) ; ++i) {
224 rc = erase_page(dev, i);
225 if (rc < 0) {
226 break;
227 }
228 }
229
230 return rc;
231 }
232
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)233 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
234 const void *data, unsigned int len)
235 {
236 int i, rc = 0;
237
238 for (i = 0; i < len; i += 8, offset += 8U) {
239 rc = write_dword(dev, offset,
240 UNALIGNED_GET((const uint64_t *) data + (i >> 3)));
241 if (rc < 0) {
242 return rc;
243 }
244 }
245
246 return rc;
247 }
248
flash_stm32_option_bytes_write(const struct device * dev,uint32_t mask,uint32_t value)249 int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
250 uint32_t value)
251 {
252 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
253 int rc;
254
255 if (regs->CR & FLASH_CR_OPTLOCK) {
256 return -EIO;
257 }
258
259 if ((regs->OPTR & mask) == value) {
260 return 0;
261 }
262
263 rc = flash_stm32_wait_flash_idle(dev);
264 if (rc < 0) {
265 return rc;
266 }
267
268 regs->OPTR = (regs->OPTR & ~mask) | value;
269 regs->CR |= FLASH_CR_OPTSTRT;
270
271 /* Make sure previous write is completed. */
272 barrier_dsync_fence_full();
273
274 rc = flash_stm32_wait_flash_idle(dev);
275 if (rc < 0) {
276 return rc;
277 }
278
279 return 0;
280 }
281
flash_stm32_option_bytes_read(const struct device * dev)282 uint32_t flash_stm32_option_bytes_read(const struct device *dev)
283 {
284 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
285
286 return regs->OPTR;
287 }
288
289 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
290
291 /*
292 * Remark for future development implementing Write Protection for the L4 parts:
293 *
294 * STM32L4 allows for 2 write protected memory areas, c.f. FLASH_WEP1AR, FLASH_WRP1BR
295 * which are defined by their start and end pages.
296 *
297 * Other STM32 parts (i.e. F4 series) uses bitmask to select sectors.
298 *
299 * To implement Write Protection for L4 one should thus add a new EX_OP like
300 * FLASH_STM32_EX_OP_SECTOR_WP_RANGED in stm32_flash_api_extensions.h
301 */
302
303 #endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
304
305 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
flash_stm32_get_rdp_level(const struct device * dev)306 uint8_t flash_stm32_get_rdp_level(const struct device *dev)
307 {
308 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
309
310 return (regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
311 }
312
flash_stm32_set_rdp_level(const struct device * dev,uint8_t level)313 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
314 {
315 flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
316 (uint32_t)level << FLASH_OPTR_RDP_Pos);
317 }
318 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
319
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)320 void flash_stm32_page_layout(const struct device *dev,
321 const struct flash_pages_layout **layout,
322 size_t *layout_size)
323 {
324 static struct flash_pages_layout stm32l4_flash_layout = {
325 .pages_count = 0,
326 .pages_size = 0,
327 };
328
329 ARG_UNUSED(dev);
330
331 if (stm32l4_flash_layout.pages_count == 0) {
332 stm32l4_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
333 stm32l4_flash_layout.pages_size = FLASH_PAGE_SIZE;
334 }
335
336 *layout = &stm32l4_flash_layout;
337 *layout_size = 1;
338 }
339
