1# Copyright 2024 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4config SOC_SERIES_MCXN 5 select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE 6 select CLOCK_CONTROL 7 select ARM 8 select HAS_MCUX 9 select HAS_MCUX_FLEXCOMM 10 select CPU_CORTEX_M_HAS_SYSTICK 11 select CPU_CORTEX_M_HAS_DWT 12 13config SOC_MCXN947_CPU0 14 select CPU_CORTEX_M33 15 select CPU_HAS_ARM_SAU 16 select CPU_HAS_ARM_MPU 17 select CPU_HAS_FPU 18 select ARMV8_M_DSP 19 select SOC_RESET_HOOK 20 select ARM_TRUSTZONE_M 21 select HAS_MCUX_CACHE 22 23config SOC_MCXN947_CPU1 24 select CPU_CORTEX_M33 25 26config SOC_MCXN236 27 select CPU_CORTEX_M33 28 select CPU_HAS_ARM_SAU 29 select CPU_HAS_ARM_MPU 30 select CPU_HAS_FPU 31 select ARMV8_M_DSP 32 select SOC_RESET_HOOK 33 select ARM_TRUSTZONE_M 34 35if SOC_SERIES_MCXN 36 37if SOC_MCXN947 38config SECOND_CORE_MCUX 39 bool "MCXN94X's second core" 40 depends on HAS_MCUX 41 help 42 Indicates the second core will be enabled, and the part will run 43 in dual core mode. 44 45config FLASH_DISABLE_CACHE64 46 bool "Disable the CACHE64 cache for FlexSPI flash accesses" 47 help 48 Disable cache64 cache. 49 50config MCUX_CORE_SUFFIX 51 default "_cm33_core0" if SOC_MCXN947_CPU0 52 default "_cm33_core1" if SOC_MCXN947_CPU1 53endif 54 55rsource "../../common/Kconfig.flexspi_xip" 56 57endif # SOC_SERIES_MCXN 58
