1# Copyright 2019,2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_SERIES_LPC55XXX
5
6config NUM_IRQS
7	# must be >= the highest interrupt number used
8	default 60
9
10config SYS_CLOCK_HW_CYCLES_PER_SEC
11	default 144000000 if INIT_PLL1
12	default 96000000
13
14# Indicates the second core will be enabled, and the part will run
15# in dual core mode.
16config SECOND_CORE_MCUX
17	depends on HAS_MCUX
18
19# Workaround for not being able to have commas in macro arguments
20DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
21
22# Move the LMA for the second core image to be in the flash region of primary
23# core, so that JLink flash will load it correctly.
24config BUILD_OUTPUT_ADJUST_LMA
25	depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
26	default "0x10000000"
27
28# SRAM controllers 1,2,3, and 4 are disabled at reset.
29# By default, CMSIS SystemInit will enable the clock to these RAM banks.
30# Disable this Kconfig to leave the ram banks untouched out of reset.
31config LPC55XXX_SRAM_CLOCKS
32	default y
33
34# Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
35# By default, USB RAM is assumed to be present.
36# Disable this Kconfig in case there is no dedicated USB RAM.
37config LPC55XXX_USB_RAM
38	default y if (!SOC_LPC55S06 && !SOC_LPC55S36)
39
40# Set to the minimal size of data which can be written.
41config FLASH_FILL_BUFFER_SIZE
42	default 512
43
44if SOC_LPC55S06
45
46endif # SOC_LPC55S06
47
48if SOC_LPC55S16
49
50config CAN_MCUX_MCAN
51	default y
52	depends on CAN
53
54endif # SOC_LPC55S16
55
56if SOC_LPC55S69_CPU0
57
58config SOC_FLASH_MCUX
59	default y
60	depends on FLASH
61	depends on !TRUSTED_EXECUTION_NONSECURE
62
63config I2S_MCUX_FLEXCOMM
64	select INIT_PLL0
65
66endif # SOC_LPC55S69_CPU0
67
68if SOC_LPC55S69_CPU1
69
70config GPIO
71	default y
72
73config SERIAL
74	default n
75
76endif # SOC_LPC55S69_CPU1
77
78endif # SOC_SERIES_LPC55XXX
79