1# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or 2# an affiliate of Cypress Semiconductor Corporation 3# SPDX-License-Identifier: Apache-2.0 4 5# Infineon CAT1A devices 6 7# Family definitions 8config SOC_FAMILY_PSOC6 9 select ARM 10 select CPU_CORTEX_M4 11 select CPU_HAS_ARM_MPU 12 select DYNAMIC_INTERRUPTS 13 select CPU_HAS_FPU 14 select SOC_FAMILY_INFINEON_CAT1 15 select BUILD_OUTPUT_HEX 16 17config SOC_FAMILY_PSOC6_LEGACY 18 select ARM 19 select HAS_CYPRESS_DRIVERS 20 select CPU_CORTEX_M_HAS_SYSTICK 21 select BUILD_OUTPUT_HEX 22 select CPU_HAS_ARM_MPU 23 24config SOC_FAMILY_PSOC6_LEGACY_M4 25 select CPU_CORTEX_M4 26 select CPU_CORTEX_M_HAS_DWT 27 select CPU_HAS_FPU 28 29config SOC_FAMILY_PSOC6_LEGACY_M0 30 select CPU_CORTEX_M0PLUS 31 select CPU_CORTEX_M_HAS_VTOR 32 33config SOC_PSOC6_M0_ENABLES_M4 34 bool "Dual-core support [activate Cortex-M4]" 35 depends on SOC_FAMILY_PSOC6_LEGACY_M0 36 help 37 Cortex-M0 CPU should boot Cortex-M4 38 39if SOC_FAMILY_PSOC6 40## PSOC™ 6 Cortex M0+ prebuilt images 41choice 42 prompt "PSOC™ 6 Cortex M0+ prebuilt images" 43 help 44 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6 45 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. 46 47config SOC_PSOC6_CM0P_IMAGE_SLEEP 48 bool "DeepSleep" 49 help 50 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE 51 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 52 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 53 linker script. 54endchoice 55 56config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE 57 hex 58 default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP 59 60config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE 61 hex 62 default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP 63 64endif # SOC_FAMILY_PSOC6 65
