1# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or 2# an affiliate of Cypress Semiconductor Corporation 3# SPDX-License-Identifier: Apache-2.0 4 5# Infineon CAT1A devices 6 7# Family definitions 8config SOC_FAMILY_PSOC6 9 select ARM 10 select CPU_CORTEX_M4 11 select CPU_HAS_ARM_MPU 12 select DYNAMIC_INTERRUPTS 13 select CPU_HAS_FPU 14 select SOC_FAMILY_INFINEON_CAT1 15 16config SOC_FAMILY_PSOC6_LEGACY 17 select ARM 18 select HAS_CYPRESS_DRIVERS 19 select CPU_CORTEX_M_HAS_SYSTICK 20 select CPU_HAS_ARM_MPU 21 22config SOC_FAMILY_PSOC6_LEGACY_M4 23 select CPU_CORTEX_M4 24 select CPU_CORTEX_M_HAS_DWT 25 select CPU_HAS_FPU 26 27config SOC_FAMILY_PSOC6_LEGACY_M0 28 select CPU_CORTEX_M0PLUS 29 select CPU_CORTEX_M_HAS_VTOR 30 31config SOC_PSOC6_M0_ENABLES_M4 32 bool "Dual-core support [activate Cortex-M4]" 33 depends on SOC_FAMILY_PSOC6_LEGACY_M0 34 help 35 Cortex-M0 CPU should boot Cortex-M4 36 37if SOC_FAMILY_PSOC6 38## PSOC™ 6 Cortex M0+ prebuilt images 39choice 40 prompt "PSOC™ 6 Cortex M0+ prebuilt images" 41 help 42 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6 43 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. 44 45config SOC_PSOC6_CM0P_IMAGE_SLEEP 46 bool "DeepSleep" 47 help 48 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE 49 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 50 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 51 linker script. 52endchoice 53 54config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE 55 hex 56 default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP 57 58config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE 59 hex 60 default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP 61 62endif # SOC_FAMILY_PSOC6 63
