1# Microchip MEC MCU line
2
3# Copyright (c) 2018, Intel Corporation
4# Copyright (c) 2022, Microchip Technology Inc.
5# SPDX-License-Identifier: Apache-2.0
6
7if SOC_FAMILY_MICROCHIP_MEC
8
9menuconfig MCHP_MEC_UNSIGNED_HEADER
10	bool "Create an unsigned output binary with MCHP MEC binary header"
11	depends on SOC_SERIES_MEC172X
12	help
13	  On Microchip MEC series chip, the ROM code loads firmware image from flash
14	  to RAM using a TAG to locate a Header which specifies the location and
15	  size of the firmware image. Enable this to invoke the mec_spi_gen tool
16	  which generates an SPI image with TAG, Header, and firmware binary. This
17	  tool does not produce a signed image which can be authenticated by the
18	  Boot-ROM. Use the full Microchip SPI image generator program for
19	  authentication and all other Boot-ROM loader features. Refer to the MCHP
20	  EVB boards for an example.
21
22if MCHP_MEC_UNSIGNED_HEADER
23
24config MCHP_MEC_HEADER_CHIP
25	string
26	default "mec15xx" if SOC_SERIES_MEC15XX
27	default "mec172x" if SOC_SERIES_MEC172X
28
29choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE
30	prompt "Clock rate to use for SPI flash"
31	default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
32	help
33	  This selects the SPI clock frequency that will be used for loading
34	  firmware binary from flash to RAM.
35
36config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
37	bool "SPI flash clock rate of 12 MHz"
38
39config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
40	bool "SPI flash clock rate of 16 MHz"
41
42config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
43	bool "SPI flash clock rate of 24 MHz"
44
45config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
46	bool "SPI flash clock rate of 48 MHz"
47
48endchoice
49
50config MCHP_MEC_HEADER_SPI_FREQ_MHZ
51	int
52	default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12
53	default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16
54	default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
55	default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48
56
57choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE
58	prompt "Reading mode used by the SPI flash"
59	default MCHP_MEC_HEADER_SPI_READ_MODE_FAST
60	help
61	  This sets the reading mode that can be used by the SPI flash.
62	  Reading modes supported are normal, fast, dual, and quad.
63
64config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
65	bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
66
67config MCHP_MEC_HEADER_SPI_READ_MODE_FAST
68	bool "SPI flash operates full-duplex with fast reading mode"
69
70config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
71	bool "SPI flash operates with dual data reading mode"
72
73config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
74	bool "SPI flash operates with quad data reading mode"
75
76endchoice
77
78config MCHP_MEC_HEADER_SPI_READ_MODE
79	string
80	default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL
81	default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST
82	default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
83	default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD
84
85choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE
86	prompt "Flash size"
87	default MCHP_MEC_HEADER_FLASH_SIZE_16M
88	help
89	  This sets the SPI flash size.
90
91config MCHP_MEC_HEADER_FLASH_SIZE_256K
92	bool "SPI flash size 256K Bytes"
93	help
94	  The SPI flash size is 256K Bytes.
95
96config MCHP_MEC_HEADER_FLASH_SIZE_512K
97	bool "SPI flash size 512K Bytes"
98	help
99	  The SPI flash size is 512K Bytes.
100
101config MCHP_MEC_HEADER_FLASH_SIZE_1M
102	bool "SPI flash size 1M Bytes"
103	help
104	  The SPI flash size is 1M Bytes.
105
106config MCHP_MEC_HEADER_FLASH_SIZE_2M
107	bool "SPI flash size 2M Bytes"
108	help
109	  The SPI flash size is 2M Bytes.
110
111config MCHP_MEC_HEADER_FLASH_SIZE_4M
112	bool "SPI flash size 4M Bytes"
113	help
114	  The SPI flash size is 4M Bytes.
115
116config MCHP_MEC_HEADER_FLASH_SIZE_8M
117	bool "SPI flash size 8M Bytes"
118	help
119	  The SPI flash size is 8M Bytes.
120
121config MCHP_MEC_HEADER_FLASH_SIZE_16M
122	bool "SPI flash size 16M Bytes"
123	help
124	  The SPI flash size is 16M Bytes.
125
126endchoice
127
128config MCHP_MEC_HEADER_FLASH_SIZE
129	int
130	default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K
131	default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K
132	default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M
133	default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M
134	default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M
135	default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M
136	default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M
137
138choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE
139	prompt "Flash drive strength"
140	default MCHP_MEC_HEADER_SPI_DRVSTR_1X
141	help
142	  This sets the SPI flash size.
143
144config MCHP_MEC_HEADER_SPI_DRVSTR_1X
145	bool "SPI flash drive strength multiplier 1"
146	help
147	  The SPI flash size is 256K Bytes.
148
149config MCHP_MEC_HEADER_SPI_DRVSTR_2X
150	bool "SPI flash drive strength multiplier 2"
151	help
152	  The SPI flash size is 256K Bytes.
153
154config MCHP_MEC_HEADER_SPI_DRVSTR_4X
155	bool "SPI flash drive strength multiplier 4"
156	help
157	  The SPI flash size is 512K Bytes.
158
159config MCHP_MEC_HEADER_SPI_DRVSTR_6X
160	bool "SPI flash drive strength multiplier 6"
161	help
162	  The SPI flash size is 1M Bytes.
163
164endchoice
165
166config MCHP_MEC_HEADER_SPI_DRVSTR
167	string
168	default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X
169	default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X
170	default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X
171	default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X
172
173choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE
174	prompt "Slew rate of SPI pins"
175	default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
176	help
177	  This sets the slew rate of the SPI pins. Default is slow
178	  slew rate which is 1/2 the AHB clock rate. Fast slew is the
179	  AHB clock rate.
180
181config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
182	bool "SPI pins slew rate is 1/2 AHB frequency"
183
184config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
185	bool "SPI pins slew rate is 1x AHB frequency"
186
187endchoice
188
189config MCHP_MEC_HEADER_SPI_SLEW_RATE
190	string
191	default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW
192	default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST
193
194config MCHP_MEC_HEADER_FLASH_SPI_MODE
195	int "Flash SPI Mode"
196	range 0 7
197	default 0
198	help
199	  This three bit value corresponds to the QMSPI controllers clock idle and
200	  input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
201	  to the data sheet. Default value is 0 corresponding to SPI Mode 0
202	  signalling.
203	  Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0
204	  Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1
205
206config MCHP_HEADER_VERBOSE_OUTPUT
207	bool "Debug console output"
208	default n
209	help
210	  Enable print output from SPI generator script for debug
211
212endif # MCHP_MEC_UNSIGNED_HEADER
213
214# Common debug configuration
215choice
216	prompt "MEC debug interface general configuration"
217	default SOC_MEC_DEBUG_AND_TRACING
218	depends on SOC_SERIES_MEC174X || SOC_SERIES_MEC175X || SOC_SERIES_MECH172X
219	help
220	  Select Debug SoC interface support for MEC SoC family
221
222	config SOC_MEC_DEBUG_DISABLED
223		bool "Disable debug support"
224		help
225		  Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
226		  pin is ignored. All other JTAG pins can be used as GPIOs
227		  or other non-JTAG alternate functions.
228
229	config SOC_MEC_DEBUG_WITHOUT_TRACING
230		bool "Debug support via Serial wire debug"
231		help
232		  JTAG port in SWD mode.
233
234	config SOC_MEC_DEBUG_AND_TRACING
235		bool "Debug support via Serial wire debug with tracing enabled"
236		help
237		  JTAG port is enabled in SWD mode.
238endchoice
239
240choice
241	prompt "MEC debug interface trace configuration"
242	default SOC_MEC_DEBUG_AND_SWV_TRACING
243	depends on SOC_MEC_DEBUG_AND_TRACING
244	help
245	  Select tracing mode for debug interface
246
247	config SOC_MEC_DEBUG_AND_ETM_TRACING
248		bool "Debug support via Serial wire debug"
249		help
250		  JTAG port in SWD mode and ETM as tracing method.
251		  ETM re-assigns 5 pins for clock and 4-bit data bus.
252		  Check data sheet for functions shared with ETM.
253
254	config SOC_MEC_DEBUG_AND_SWV_TRACING
255		bool "debug support via Serial Wire Debug and Viewer"
256		help
257		  JTAG port in SWD mode and SWV as tracing method.
258		  Check data sheet for functions shared with SWD and SWV pins.
259endchoice
260
261# common processor clock divider configuration
262config SOC_MEC_PROC_CLK_DIV
263	int "PROC_CLK_DIV"
264	default 1
265	range 1 48
266	help
267	  This divisor defines a ratio between processor clock (HCLK)
268	  and main 96 MHz clock (MCK):
269	  HCLK = MCK / PROC_CLK_DIV
270	  Allowed divider values: 1, 3, 4, 16, and 48.
271
272# Select SoC Part No. and configuration options
273rsource "*/Kconfig"
274
275endif # SOC_FAMILY_MICROCHIP_MEC
276