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/Zephyr-latest/boards/quicklogic/qomu/
Dqomu.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &uart1;
20 zephyr,uart-pipe = &uart1;
31 compatible = "gpio-leds";
49 compatible = "gpio-keys";
65 input-enable;
69 output-enable;
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dquicklogic,eos-s3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
18 input-enable;
22 output-enable;
26 compatible: "quicklogic,eos-s3-pinctrl"
34 child-binding:
40 - name: pincfg-node.yaml
41 property-allowlist:
42 - input-enable
43 - output-enable
[all …]
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 pin function selection and pin properties. For example, you can use these
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
15 - pinmux-locked: Lock pinmux configuration for peripheral device
16 - pinmux-gpio: Inverse pinmux back to gpio
17 - psl-in-mode: Select the assertion detection mode of PSL input
18 - psl-in-pol: Select the assertion detection polarity of PSL input
23 #include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
[all …]
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 RT600/RT500 pin control node. This node defines pin configurations in pin
17 slew-rate = "normal";
18 drive-strength = "normal";
24 IOCON_FUNC=<pin mux selection>,
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
[all …]
Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
[all …]
Dinfineon,cat1-pinctrl.yaml4 # SPDX-License-Identifier: Apache-2.0
9 This is a singleton node responsible for controlling the pin function selection
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
[all …]
Dnxp,mci-io-mux.yaml2 # SPDX-License-Identifier: Apache-2.0
5 MCI IO MUX pin control node. This node defines pin configurations in pin
17 slew-rate = "normal";
30 bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
31 bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)
33 compatible: "nxp,mci-io-mux"
36 - name: base.yaml
38 child-binding:
40 child-binding:
44 - name: pincfg-node.yaml
[all …]
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
32 /* Configure GPIO to push-pull mode */
33 drive-push-pull;
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
22 /* gpio port control register (byte mapping to pin) */
24 /* port driving select control */
26 /* function 3 general control register */
30 /* function 3 external control register */
34 /* function 4 general control register */
38 /* Input voltage selection */
40 /* Input voltage selection mask */
46 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
50 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
[all …]
/Zephyr-latest/dts/bindings/video/
Dovti,ov2640.yaml2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
19 Define the value to the Clock Rate Control register. By changing
22 Bit[7] Internal frequency doublers ON/OFF selection.
29 include: i2c-device.yaml
/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
110 /* Disable Smart TX Power control */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
123 /* Automatic Acknowledgement Pending bit control */
126 /* System Time Counter (40-bit) */
[all …]
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
7 /* Port 0~4 PHY Control Register. */
23 /* Link speed selection offset. */
44 /* Address Table Control And Status Register PHY Address */
46 /* Address Table Control And Status Register Register SAddress */
101 /* WoL Control Register PHY Address */
103 /* WoL Control Register Register Address */
114 /* Interrupt Mask & Control Register PHY Address. */
116 /* Interrupt Mask & Control Register Register Address. */
120 /* Port 5 Force Speed control bit */
[all …]
/Zephyr-latest/modules/segger/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
10 Indicates that the platform supports SEGGER J-Link RTT.
17 Enable Segger J-Link RTT libraries for platforms that support it.
18 Selection of this option enables use of RTT for various subsystems.
29 int "Maximum number of up-buffers"
33 int "Maximum number of down-buffers"
45 int "Size of buffer for RTT printf to bulk-send chars via RTT"
49 prompt "Mode for pre-initialized terminal channel (buffer 0)"
70 bool "Use a simple byte-loop instead of standard memcpy"
108 RTT initialization function can avoid re-init of Control Block
[all …]
/Zephyr-latest/soc/ite/ec/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
18 /* Pinmux control group */
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
41 * Pin pull-up/down config [ 4 : 5 ]
42 * Pin voltage selection [ 8 ]
44 * Pin push-pull/open-drain [ 16 ]
60 /* Pin tri-state mode. */
63 /* Pin pull-up or pull-down */
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_ps2.h4 * SPDX-License-Identifier: Apache-2.0
15 * Writes -> Transmit buffer
16 * Read <- Receive buffer
20 /* PS2 Control register */
32 /* Protocol parity selection */
41 /* Protocol stop bit selection */
54 /* RX Data Ready(Read-Only) */
66 /* Transmitter is Idle(Read-Only) */
72 /* RX is Busy(Read-Only) */
/Zephyr-latest/drivers/led/
Dis31fl3733.c2 * Copyright 2022-2023 Daniel DeGrasse <daniel@degrasse.com>
4 * SPDX-License-Identifier: Apache-2.0
19 #define CMD_SEL_REG 0xFD /* Command/page selection reg */
24 #define CMD_LOCK_REG 0xFE /* Command selection lock reg */
36 #define GLOBAL_CURRENT_CTRL_REG 0x1 /* global current control register */
70 const struct is31fl3733_config *config = dev->config; in is31fl3733_select_page()
71 struct is31fl3733_data *data = dev->data; in is31fl3733_select_page()
74 if (data->selected_page == page) { in is31fl3733_select_page()
79 /* Unlock page selection register */ in is31fl3733_select_page()
80 ret = i2c_reg_write_byte_dt(&config->bus, CMD_LOCK_REG, CMD_LOCK_UNLOCK); in is31fl3733_select_page()
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dite,it8xxx2-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 has-volt-sel:
17 Selection of support input voltage 3.3V or 1.8V.
19 wuc-base:
24 a wake-up signal to the INTC, allowing the CPU to exit
27 wuc-mask:
30 keyboard-controller:
37 when the judgment of gpio_config->ksb_ctrl is true.
[all …]
/Zephyr-latest/soc/ene/kb1200/reg/
Dgcfg.h4 * SPDX-License-Identifier: Apache-2.0
18 volatile uint32_t MCURST; /*MCU Reset Control Register */
23 volatile uint16_t GPIOMUX; /*GPIO MUX Control Register */
25 volatile uint16_t I2CSPMS; /*I2CS Pin Map Selection Register */
Dgpio.h4 * SPDX-License-Identifier: Apache-2.0
14 volatile uint32_t GPIOFS; /*Function Selection Register */
28 volatile uint32_t GPIODC; /*Driving Control Register */
40 /*-- Constant Define --------------------------------------------*/
/Zephyr-latest/modules/hostap/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
49 # l2_packet - 1
50 # ctrl_iface - 2 * socketpairs = 4(local and global)
51 # z_wpa_event_sock - 1 socketpair = 2
54 # Supplicant API is stack heavy (buffers + snprintfs) and control interface
59 module-str = WPA supplicant
63 int "Min compiled-in debug message level for WPA supplicant"
71 is compiled-in the firmware. See wpa_debug.h file of the supplicant for
73 runtime filtering can also be configured in addition to the compile-time
193 bool "EAP-TLS support"
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dvideo-controls.h5 * SPDX-License-Identifier: Apache-2.0
21 * The Video control IDs (CIDs) are introduced with the same name as
23 * inter-operability and debugging devices end-to-end across Linux and
27 * @c linux/include/uapi/linux/v4l2-controls.h
37 * @name Base class control IDs
106 * @name Camera Flash class control IDs
116 * @name JPEG class control IDs
129 * @name Image Source class control IDs
139 * @name Image Processing class control IDs
144 /** Pixel rate (pixels/second) in the device's pixel array. This control is read-only. */
[all …]
/Zephyr-latest/dts/bindings/rtc/
Dnxp,pcf8523.yaml1 # Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
11 - name: pm.yaml
12 property-allowlist:
13 - wakeup-source
16 quartz-load-femtofarads:
19 - 7000
20 - 12500
[all …]
/Zephyr-latest/subsys/mgmt/mcumgr/transport/
DKconfig.udp2 # Copyright Nordic Semiconductor ASA 2020-2022. All rights reserved.
3 # SPDX-License-Identifier: Apache-2.0
6 # subsystem and provides Kconfig options to control aspects of
62 MCUMGR_TRANSPORT_UDP_MTU <= MCUMGR_TRANSPORT_NETBUF_SIZE + SMP msg overhead - address size
63 where address size is determined by IPv4/IPv6 selection.
/Zephyr-latest/samples/boards/nordic/dynamic_pinctrl/
DREADME.rst1 .. zephyr:code-sample:: nrf_dynamic_pinctrl
2 :name: Dynamic Pin Control
6 The Dynamic Pin Control (nRF) sample demonstrates how to change ``uart0`` at
8 push-button.
22 The Dynamic Pin Control (nRF) sample allows you to select the appropriate routing.
38 .. figure:: images/nrf52840dk-dynamic-pinctrl.webp
54 .. zephyr-app-commands::
55 :zephyr-app: samples/boards/nordic/dynamic_pinctrl
69 1. Connect a USB-to-UART adapter to both sets of pins. If the board routes the
76 .. figure:: images/terminals-empty.png
[all …]
/Zephyr-latest/doc/develop/test/twister/
Dsample_blackbox_test.py4 # SPDX-License-Identifier: Apache-2.0
48 # * Control the level of detail in stdout/err
51 # * Control whether to only build or build and run aforementioned tests
52 ["-i", "--outdir", out_path, "-T", path, "-y"]
54 + ["--level", level]
56 + ["--test-config", config_path]
57 # Flags related to platform selection
60 for pair in zip(["-p"] * len(test_platforms), test_platforms, strict=False)
92 # Test-relevant checks

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