1# Copyright 2022, NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  RT600/RT500 pin control node. This node defines pin configurations in pin
6  groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
7  group within the pin configuration defines a peripheral's pin configuration.
8  Each numbered subgroup represents pins with shared configuration for that
9  peripheral. The 'pinmux' property of each group selects the pins to be
10  configured with these properties. For example, here is a configuration
11  for FLEXCOMM0 pins:
12
13  pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
14    group0 {
15      pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_1>,
16              <FC0_RXD_SDA_MOSI_DATA_PIO0_2>;
17      slew-rate = "normal";
18      drive-strength = "normal";
19    };
20  };
21
22  If only the required properties are supplied, the ICON_PIO register will
23  be assigned the following values:
24  IOCON_FUNC=<pin mux selection>,
25  IOCON_PUPDENA = 0,
26  IOCON_PUPDSEL = 0,
27  IOCON_IBENA = 0,
28  IOCON_SLEWRATE = <slew-rate selection>,
29  IOCON_FULLDRIVE = <drive-strength selection>,
30  IOCON_AMENA = 0,
31  IOCON_ODENA = 0,
32  IOCON_IIENA = 0,
33
34  Note the inherited pinctrl properties defined below have the following effects:
35  drive-open-drain: IOCON_ODENA=1
36  bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37  bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38  input-enable: IOCON_IBENA=1
39
40compatible: "nxp,rt-iocon-pinctrl"
41
42include: base.yaml
43
44child-binding:
45  description: iMX RT IOCON pin controller pin group
46  child-binding:
47    description: |
48      iMX RT IOCON pin controller pin configuration node
49
50    include:
51      - name: pincfg-node.yaml
52        property-allowlist:
53          - drive-open-drain
54          - bias-pull-up
55          - bias-pull-down
56          - input-enable
57
58    properties:
59      pinmux:
60        required: true
61        type: array
62        description: |
63          Pin mux selection for this group. See the SOC level pinctrl header
64          file in NXP's HAL for a defined list of these options.
65      slew-rate:
66        required: true
67        type: string
68        enum:
69          - "normal"
70          - "slow"
71        description: |
72          Pin output slew rate. Sets the SLEWRATE field in the IOCON register.
73          0 SLEWRATE_0- normal mode, output slew rate is standard
74          1 SLEWRATE_1- slow mode, output slew rate is slower
75      drive-strength:
76        required: true
77        type: string
78        enum:
79          - "normal"
80          - "high"
81        description: |
82          Pin output drive strength. Sets the FULLDRIVE field in the
83          IOCON register.
84          0 FULLDRIVE_0- Normal output drive mode
85          1 FULLDRIVE_1- Full output drive mode, output strength is twice
86          the drive strength of normal drive mode.
87      nxp,invert:
88        type: boolean
89        description: |
90          Invert the pin input logic level
91      nxp,analog-mode:
92        type: boolean
93        description: |
94          Set the pin to analog mode. Sets AMENA=1
95