1# Copyright (c) 2024 Silicon Labs
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    The Silabs pin controller is a singleton node responsible for controlling
6    pin function selection and pin properties. For example, you can use this
7    node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8    pin. This pin controller is used for devices that use DBUS (Digital Bus)
9    for alternate function configuration, including Series 2 devices.
10
11    The pinctrl settings are referenced in a device tree peripheral node. For
12    example when configuring a USART:
13
14      &usart0 {
15        compatible = "silabs,gecko-usart";
16        pinctrl-0 = <&usart0_default>;
17        pinctrl-names = "default";
18      }
19
20    pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
21    this example &usart0_default. This phandle is defined as a child node of the
22    'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
23    directory or a device tree overlay in the application:
24
25      &pinctrl {
26        /* Configuration for USART0 peripheral, default state */
27        usart0_default: usart0_default {
28          /* Group of output pins with shared properties (name is arbitrary) */
29          group0 {
30            /* Configure PA8 as USART0 TX in GPIO DBUS */
31            pins = <USART0_TX_PA8>;
32            /* Configure GPIO to push-pull mode */
33            drive-push-pull;
34            /* Set DOUT high */
35            output-high;
36          };
37          /* Group of input pins with shared properties (name is arbitrary) */
38          group1 {
39            /* Configure PA9 as USART0 RX in GPIO DBUS */
40            pins = <USART0_RX_PA9>;
41            /* Configure GPIO to input mode */
42            input-enable;
43            /* Enable input glitch filter */
44            silabs,input-filter;
45          };
46        };
47      };
48
49    The 'usart0_default' child node encodes the pin configurations for a
50    particular state of the device, the default (active) state.
51
52    Pin configurations are organized in groups within each child node. Each
53    group can specify a list of pin function selections in the `pins` property,
54    that all will be configured with the same GPIO mode as given by the rest
55    of the properties on the group.
56
57    The possible pin properties are as follows:
58
59    - input-disable: Configure GPIO to disabled mode. Setting this property is
60                     optional, as pins are disabled by default. If the "Input
61                     disabled with pull-up" mode is desired, the property must
62                     be set in combination with bias-pull-up.
63    - input-enable: Configure GPIO to input mode.
64    - drive-push-pull: Configure GPIO to push-pull mode.
65    - drive-open-drain: Configure GPIO to open-drain (wired-AND) mode.
66    - drive-open-source: Configure GPIO to open-source (wired-OR) mode.
67
68    Only one of the above properties must be set at a time, as they are mutually
69    exclusive. Additional properties may be combined with the above ones:
70
71    - bias-pull-down: Enable pull-down resistor. Allowed in input-enable and
72                      drive-open-source modes.
73    - bias-pull-up: Enable pull-up resistor. Allowed in input-disable,
74                    input-enable and drive-open-drain modes.
75    - output-high: Drive GPIO high. Allowed in drive-push-pull mode.
76    - output-low: Drive GPIO low. Allowed in drive-push-pull mode. Setting
77                  this property is optional, leaving it out has the same effect.
78    - silabs,input-filter: Enable input glitch filter. Allowed in input-enable
79                           and drive-open-drain modes.
80    - silabs,alternate-port-control: Use alternate port control settings.
81                                     Allowed in drive-push-pull and
82                                     drive-open-drain modes.
83
84compatible: "silabs,dbus-pinctrl"
85
86include: base.yaml
87
88child-binding:
89  description: |
90    Silabs DBUS pin controller pin configuration. Each child node defines
91    the configuration for a particular group of pins.
92  child-binding:
93    description: |
94      Silabs DBUS pin controller pin configuration group.
95    include:
96      - name: pincfg-node.yaml
97        property-allowlist:
98          - bias-pull-down
99          - bias-pull-up
100          - drive-open-drain
101          - drive-open-source
102          - drive-push-pull
103          - input-disable
104          - input-enable
105          - output-high
106          - output-low
107
108    properties:
109      pins:
110        required: true
111        type: array
112        description: |
113          An array of pins sharing the same group properties. The pins should be
114          defined using the <peripheral>_<signal>_<pin> macros available from
115          the SoC DeviceTree files.
116
117      silabs,input-filter:
118        description: |
119          Enable input glitch filter on this pin. May be used in input-enable
120          and drive-open-drain modes.
121        type: boolean
122
123      silabs,alternate-port-control:
124        description: |
125          Use Alternate Port Control settings for Slew Rate and Input Disable
126          for this pin. May be used in drive-push-pull and drive-open-drain
127          modes.
128        type: boolean
129